Publications
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2024
KLHŮFEK Jan, ŠAFÁŘ Miroslav, MRÁZEK Vojtěch, VAŠÍČEK Zdeněk and SEKANINA Lukáš. Exploiting Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. In: 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS). Kielce: Institute of Electrical and Electronics Engineers, 2024, pp. 1-6. ISBN 979-8-3503-5934-3.
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2022
KLHŮFEK Jan and MRÁZEK Vojtěch. ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators. In: 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '22). Prague: Institute of Electrical and Electronics Engineers, 2022, pp. 44-47. ISBN 978-1-6654-9431-1.
Detail