Jiří Matyáš

Publications

• 2022

  ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch and VOJNAR Tomáš. Designing Approximate Arithmetic Circuits with Combined Error Constraints. In: Proceeding of 25th Euromicro Conference on Digital System Design 2022 (DSD'22). Gran Canaria: Institute of Electrical and Electronics Engineers, 2022, pp. 785-792. ISBN 978-1-6654-7404-7.
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  ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. SagTree: Towards Efficient Mutation in Evolutionary Circuit Approximation. Swarm and Evolutionary Computation, vol. 69, no. 100986, 2022, pp. 1-10. ISSN 2210-6502.
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• 2020

  ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. Applied Soft Computing, vol. 95, no. 106466, 2020, pp. 1-17. ISSN 1568-4946.
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  MATYÁŠ Jiří, PANKUCH Adam, VOJNAR Tomáš, ČEŠKA Milan and ČEŠKA Milan. Approximating Complex Arithmetic Circuits with Guaranteed Worst-Case Relative Error. In: International Conference on Computer Aided Systems Theory (EUROCAST'19). Lecture Notes in Computer Science, vol. 12013. Cham: Springer Verlag, 2020, pp. 482-490. ISBN 978-3-030-45092-2.
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  ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch and VOJNAR Tomáš. Satisfiability Solving Meets Evolutionary Optimisation in Designing Approximate Circuits. In: Theory and Applications of Satisfiability Testing - SAT 2020. Lecture Notes in Computer Science, vol. 12178. Alghero: Springer International Publishing, 2020, pp. 481-491. ISBN 978-3-030-51824-0.
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• 2018

  ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. ADAC: Automated Design of Approximate Circuits. In: Proceedings of 30th International Conference on Computer Aided Verification (CAV'18). Oxford, UK: Springer International Publishing, 2018, pp. 612-620. ISBN 978-3-319-96145-3.
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• 2017

  ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished. In: Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD). Irvine, CA: Institute of Electrical and Electronics Engineers, 2017, pp. 416-423. ISBN 978-1-5386-3093-8.
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