Vojtěch Mrázek

Publications

• 2024

  DENIZIAK Stanisław, SITEK Paweł, JENIHHIN Maksim, STEININGER Andreas, SCHÖLZEL Mario and MRÁZEK Vojtěch, ed. 27th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Kliece: Institute of Electrical and Electronics Engineers, 2024. ISBN 979-8-3503-5934-3.
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  PIŇOS Michal, SEKANINA Lukáš and MRÁZEK Vojtěch. ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. In: 2024 The International Joint Conference on Neural Networks (IJCNN). Yokohama: Institute of Electrical and Electronics Engineers, 2024, pp. 1-8. ISBN 979-8-3503-5931-2.
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  VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. In: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE). Valencia: Institute of Electrical and Electronics Engineers, 2024, pp. 1-6. ISBN 979-8-3503-4859-0.
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  ŠÍMA Jiří, MRÁZEK Vojtěch and VIDNEROVÁ Petra. Energy Complexity of Convolutional Neural Networks. Neural Computation, vol. 36, no. 8, 2024, pp. 1601-1625. ISSN 0899-7667.
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  MRÁZEK Vojtěch, KOKKINIS Argyrios, PAPANIKOLAOU Panagiotis, VAŠÍČEK Zdeněk, SIOZIOS Kostas, TZIMPRAGOS Georgios, TAHOORI Mehdi and ZERVAKIS Georgios. Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks. In: 2024 IEEE/ACM International Conference on Computer Aided Design (ICCAD). New Jersey, 2024, p. 9.
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  KLHŮFEK Jan, ŠAFÁŘ Miroslav, MRÁZEK Vojtěch, VAŠÍČEK Zdeněk and SEKANINA Lukáš. Exploiting Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. In: 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS). Kielce: Institute of Electrical and Electronics Engineers, 2024, pp. 1-6. ISBN 979-8-3503-5934-3.
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• 2023

  PIŇOS Michal, MRÁZEK Vojtěch, VAVERKA Filip, VAŠÍČEK Zdeněk and SEKANINA Lukáš. Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 13, no. 1, 2023, pp. 212-224. ISSN 2156-3357.
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  HURTA Martin, MRÁZEK Vojtěch, DRAHOŠOVÁ Michaela and SEKANINA Lukáš. ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. In: 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE). Antwerp: Institute of Electrical and Electronics Engineers, 2023, pp. 1-2. ISBN 978-3-9819263-7-8.
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  MRÁZEK Vojtěch. Approximation of Hardware Accelerators driven by Machine-Learning Models. In: Proceedings of International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '23). Tallinn: Institute of Electrical and Electronics Engineers, 2023, pp. 91-92. ISBN 979-8-3503-3277-3.
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  MRÁZEK Vojtěch, JAWED Soyiba, ARIF Muhammad and MALIK Aamir Saeed. Effective EEG Feature Selection for Interpretable MDD (Major Depressive Disorder) Classification. In: GECCO 2023 - Proceedings of the 2023 Genetic and Evolutionary Computation Conference. Lisbon: Association for Computing Machinery, 2023, pp. 1427-1435. ISBN 979-8-4007-0119-1.
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  ŠÍMA Jiří, VIDNEROVÁ Petra and MRÁZEK Vojtěch. Energy Complexity Model for Convolutional Neural Networks. In: Artificial Neural Networks and Machine Learning - ICANN 2023: 32nd International Conference on Artificial Neural Networks. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Heraklion, 2023, pp. 186-198. ISBN 978-3-031-44203-2.
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  SEKANINA Lukáš, MRÁZEK Vojtěch and PIŇOS Michal. Hardware-Aware Evolutionary Approaches to Deep Neural Networks. Handbook of Evolutionary Machine Learning. Genetic and Evolutionary Computation. Singapore: Springer Nature Singapore, 2023, pp. 367-396. ISBN 978-981-9938-13-1.
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  HURTA Martin, MRÁZEK Vojtěch, DRAHOŠOVÁ Michaela and SEKANINA Lukáš. MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. In: 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Tallinn: Institute of Electrical and Electronics Engineers, 2023, pp. 155-160. ISBN 979-8-3503-3277-3.
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  HURTA Martin, MRÁZEK Vojtěch, DRAHOŠOVÁ Michaela and SEKANINA Lukáš. Multi-objective Design of Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. Evo* 2023 -- Late-Breaking Abstracts Volume. Brno, 2023.
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  PIŇOS Michal, MRÁZEK Vojtěch and SEKANINA Lukáš. Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. In: 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Talinn: Institute of Electrical and Electronics Engineers, 2023, pp. 45-50. ISBN 979-8-3503-3277-3.
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  PRABAKARAN Bharath S., MRÁZEK Vojtěch, VAŠÍČEK Zdeněk, SEKANINA Lukáš and SHAFIQUE Muhammad. Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. In: 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD). San Francisco: Institute of Electrical and Electronics Engineers, 2023, pp. 1-9. ISBN 979-8-3503-1559-2.
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• 2022

  HANIF Muhammad A., MRÁZEK Vojtěch and SHAFIQUE Muhammad. Approximate Computing Architectures. Handbook of Computer Architecture. Handbook of Computer Architecture. Singapore: Springer Nature Singapore, 2022, pp. 1-41. ISBN 978-981-1564-01-7.
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  KLHŮFEK Jan and MRÁZEK Vojtěch. ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators. In: 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '22). Prague: Institute of Electrical and Electronics Engineers, 2022, pp. 44-47. ISBN 978-1-6654-9431-1.
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  ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch and VOJNAR Tomáš. Designing Approximate Arithmetic Circuits with Combined Error Constraints. In: Proceeding of 25th Euromicro Conference on Digital System Design 2022 (DSD'22). Gran Canaria: Institute of Electrical and Electronics Engineers, 2022, pp. 785-792. ISBN 978-1-6654-7404-7.
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  PIŇOS Michal, MRÁZEK Vojtěch and SEKANINA Lukáš. Evolutionary Approximation and Neural Architecture Search. Genetic Programming and Evolvable Machines, vol. 23, no. 3, 2022, pp. 351-374. ISSN 1389-2576.
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  HURTA Martin, DRAHOŠOVÁ Michaela and MRÁZEK Vojtěch. Evolutionary Design of Reduced Precision Preprocessor for Levodopa-Induced Dyskinesia Classifier. In: Parallel Problem Solving from Nature - PPSN XVII. Lecture Notes in Computer Science, vol. 13398. Dortmund: Springer Nature Switzerland AG, 2022, pp. 491-504. ISBN 978-3-031-14713-5.
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  SEKANINA Lukáš, VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Inexact Arithmetic Operators. Approximate Computing Techniques. Cham: Springer International Publishing, 2022, pp. 81-107. ISBN 978-3-030-94704-0.
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  MRÁZEK Vojtěch. Optimization of BDD-based Approximation Error Metrics Calculations. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI '22). Paphos: Institute of Electrical and Electronics Engineers, 2022, pp. 86-91. ISBN 978-1-6654-6605-9.
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  MARCHISIO Alberto, MRÁZEK Vojtěch, MASSA Andrea, BUSSOLINO Beatrice, MARTINA Mauricio and SHAFIQUE Muhammad. RoHNAS: A Neural Architecture Search Framework with Conjoint Optimization for Adversarial Robustness and Hardware Efficiency of Convolutional and Capsule Networks. IEEE Access, vol. 2022, no. 10, pp. 109043-109055. ISSN 2169-3536.
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  ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. SagTree: Towards Efficient Mutation in Evolutionary Circuit Approximation. Swarm and Evolutionary Computation, vol. 69, no. 100986, 2022, pp. 1-10. ISSN 2210-6502.
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• 2021

  SHAFIQUE Muhammad, STEININGER Andreas, SEKANINA Lukáš, KRSTIĆ Miloš, STOJANOVIC Goran and MRÁZEK Vojtěch, ed. 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. USA: Institute of Electrical and Electronics Engineers, 2021. ISBN 978-1-6654-3595-6.
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  MARCHISIO Alberto, MRÁZEK Vojtěch, HANIF Muhammad A. and SHAFIQUE Muhammad. DESCNet: Developing Efficient Scratchpad Memories for Capsule Network Hardware. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 9, 2021, pp. 1768-1781. ISSN 1937-4151.
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  PIŇOS Michal, MRÁZEK Vojtěch and SEKANINA Lukáš. Evolutionary Neural Architecture Search Supporting Approximate Multipliers. In: Genetic Programming, 24th European Conference, EuroGP 2021. Lecture Notes in Computer Science, vol 12691, vol. 12691. Seville: Springer Nature Switzerland AG, 2021, pp. 82-97. ISBN 978-3-030-72812-0.
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  MARCHISIO Alberto, MRÁZEK Vojtěch, HANIF Muhammad A. and SHAFIQUE Muhammad. FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 4, 2021, pp. 716-729. ISSN 1063-8210.
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  HODAŇ David, MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. Genetic Programming and Evolvable Machines, vol. 22, no. 4, 2021, pp. 539-572. ISSN 1389-2576.
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• 2020

  COLUCCI Alessio, MARCHISIO Alberto, BUSSOLINO Beatrice, MRÁZEK Vojtěch, MARTINA Mauricio, MASERA Guido and SHAFIQUE Muhammad. A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress. In: 2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)}. Singapore: Institute of Electrical and Electronics Engineers, 2020, pp. 34-36. ISBN 978-1-7281-9198-0.
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  ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. Applied Soft Computing, vol. 95, no. 106466, 2020, pp. 1-17. ISSN 1568-4946.
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  PRABAKARAN Bharath S., MRÁZEK Vojtěch, VAŠÍČEK Zdeněk, SEKANINA Lukáš and SHAFIQUE Muhammad. ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems. In: 2020 57th ACM/IEEE Design Automation Conference (DAC). San Francisco: Institute of Electrical and Electronics Engineers, 2020, pp. 1-6. ISBN 978-1-4503-6725-7.
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  ANSARI Mohammad S., MRÁZEK Vojtěch, COCKBURN Bruce F., SEKANINA Lukáš, VAŠÍČEK Zdeněk and HAN Jie. Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 2, 2020, pp. 317-328. ISSN 1063-8210.
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  MRÁZEK Vojtěch, SEKANINA Lukáš and VAŠÍČEK Zdeněk. Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 10, no. 4, 2020, pp. 406-418. ISSN 2156-3357.
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  MARCHISIO Alberto, MASSA Andrea, MRÁZEK Vojtěch, BUSSOLINO Beatrice, MARTINA Mauricio and SHAFIQUE Muhammad. NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD '20). Virtual Event: Association for Computing Machinery, 2020, pp. 1-9. ISBN 978-1-4503-8026-3.
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  MARCHISIO Alberto, MRÁZEK Vojtěch, HANIF Muhammad A. and SHAFIQUE Muhammad. ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations. In: Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. Grenoble: Institute of Electrical and Electronics Engineers, 2020, pp. 1205-1210. ISBN 978-3-9819263-4-7.
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  ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch and VOJNAR Tomáš. Satisfiability Solving Meets Evolutionary Optimisation in Designing Approximate Circuits. In: Theory and Applications of Satisfiability Testing - SAT 2020. Lecture Notes in Computer Science, vol. 12178. Alghero: Springer International Publishing, 2020, pp. 481-491. ISBN 978-3-030-51824-0.
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  HODAŇ David, MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Semantically-Oriented Mutation Operator in Cartesian Genetic Programming for Evolutionary Circuit Design. In: GECCO 2020 - Proceedings of the 2020 Genetic and Evolutionary Computation Conference. Cancún: Association for Computing Machinery, 2020, pp. 940-948. ISBN 978-1-4503-7128-5.
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  VAVERKA Filip, MRÁZEK Vojtěch, VAŠÍČEK Zdeněk and SEKANINA Lukáš. TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). Grenoble: Institute of Electrical and Electronics Engineers, 2020, pp. 294-297. ISBN 978-3-9819263-4-7.
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  MRÁZEK Vojtěch, SEKANINA Lukáš and VAŠÍČEK Zdeněk. Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. In: 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems. Genoa: Institute of Electrical and Electronics Engineers, 2020, pp. 243-247. ISBN 978-1-7281-4922-6.
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• 2019

  MRÁZEK Vojtěch, VAŠÍČEK Zdeněk, SEKANINA Lukáš, HANIF Muhammad A. and SHAFIQUE Muhammad. ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Denver: Institute of Electrical and Electronics Engineers, 2019, pp. 1-8. ISBN 978-1-7281-2350-9.
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  MRÁZEK Vojtěch, HANIF Muhammad A., VAŠÍČEK Zdeněk, SEKANINA Lukáš and SHAFIQUE Muhammad. autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. In: The 56th Annual Design Automation Conference 2019 (DAC '19). Las Vegas: Association for Computing Machinery, 2019, pp. 1-6. ISBN 978-1-4503-6725-7.
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  VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Automated Circuit Approximation Method Driven by Data Distribution. In: Design, Automation and Test in Europe Conference. Florence: European Design and Automation Association, 2019, pp. 96-101. ISBN 978-3-9819263-2-3.
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  SEKANINA Lukáš, VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Automated Search-Based Functional Approximation for Digital Circuits. Approximate Circuits - Methodologies and CAD. Heidelberg: Springer International Publishing, 2019, pp. 175-203. ISBN 978-3-319-99322-5.
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  MRÁZEK Vojtěch, SEKANINA Lukáš, DOBAI Roland, SÝS Marek and ŠVENDA Petr. Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 12, 2019, pp. 2734-2744. ISSN 1063-8210.
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• 2018

  ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. ADAC: Automated Design of Approximate Circuits. In: Proceedings of 30th International Conference on Computer Aided Verification (CAV'18). Oxford, UK: Springer International Publishing, 2018, pp. 612-620. ISBN 978-3-319-96145-3.
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  MRÁZEK Vojtěch, VAŠÍČEK Zdeněk and SEKANINA Lukáš. Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. In: Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems. Edinburgh: Institute of Electrical and Electronics Engineers, 2018, pp. 264-271. ISBN 978-1-5386-7753-7.
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  SEKANINA Lukáš, MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. In: 25th IEEE International Conference on Electronics Circuits and Systems (ICECS). Bordeaux: IEEE Circuits and Systems Society, 2018, pp. 377-380. ISBN 978-1-5386-9562-3.
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  MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Evolutionary Design of Large Approximate Adders Optimized for Various Error Criteria. In: Proceedings of the Genetic and Evolutionary Computation Conference Companion (GECCO '18). Kyoto: Association for Computing Machinery, 2018, pp. 294-295. ISBN 978-1-4503-5764-7.
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  MRÁZEK Vojtěch, SÝS Marek, VAŠÍČEK Zdeněk, SEKANINA Lukáš and MATYÁŠ Václav. Evolving Boolean Functions for Fast and Efficient Randomness Testing. In: Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '18). Kyoto: Association for Computing Machinery, 2018, pp. 1302-1309. ISBN 978-1-4503-5618-3.
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  MRÁZEK Vojtěch, VAŠÍČEK Zdeněk and HRBÁČEK Radek. Role of circuit representation in evolutionary design of energy-efficient approximate circuits. IET Computers & Digital Techniques, vol. 2018, no. 4, pp. 139-149. ISSN 1751-8601.
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  MRÁZEK Vojtěch, VAŠÍČEK Zdeněk, SEKANINA Lukáš, JIANG Honglan and HAN Jie. Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 11, 2018, pp. 2572-2576. ISSN 1063-8210.
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• 2017

  SHAFIQUE Muhammad, HAFIZ Rehan, JAVED Muhammad Usama, ABBAS Sarmad, SEKANINA Lukáš, VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. In: 2017 IEEE Computer Society Annual Symposium on VLSI. Los Alamitos: IEEE Computer Society Press, 2017, pp. 627-632. ISBN 978-1-5090-6762-6.
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  SEKANINA Lukáš, VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Approximate Circuits in Low-Power Image and Video Processing: The Approximate Median Filter. Radioengineering, vol. 26, no. 3, 2017, pp. 623-632. ISSN 1210-2512.
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  ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished. In: Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD). Irvine, CA: Institute of Electrical and Electronics Engineers, 2017, pp. 416-423. ISBN 978-1-5386-3093-8.
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  MRÁZEK Vojtěch, HRBÁČEK Radek, VAŠÍČEK Zdeněk and SEKANINA Lukáš. EvoApprox8b: Library of Approximate Adders and Multipliers for Circuit Design and Benchmarking of Approximation Methods. In: Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017, pp. 258-261. ISBN 978-3-9815370-9-3.
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  MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Parallel Optimization of Transistor Level Circuits using Cartesian Genetic Programming. In: GECCO Companion '17 Proceedings of the Companion Publication of the 2017 on Genetic and Evolutionary Computation Conference. Berlin: Association for Computing Machinery, 2017, pp. 1849-1856. ISBN 978-1-4503-4939-0.
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  VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Towards Low Power Approximate DCT Architecture for HEVC Standard. In: Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017, pp. 1576-1581. ISBN 978-3-9815370-9-3.
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  VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Trading between Quality and Non-functional Properties of Median Filter in Embedded Systems. Genetic Programming and Evolvable Machines, vol. 18, no. 1, 2017, pp. 45-82. ISSN 1389-2576.
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• 2016

  HRBÁČEK Radek, MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Automatic Design of Approximate Circuits by Means of Multi-Objective Evolutionary Algorithms. In: Proceedings of the 11th International Conference on Design & Technology of Integrated Systems in Nanoscale Era. Istanbul: Istanbul Sehir University, 2016, pp. 239-244. ISBN 978-1-5090-0335-8.
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  MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Automatic Design of Arbitrary-Size Approximate Sorting Networks with Error Guarantee. In: Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016 26rd International Workshop on. Bremen: Institute of Electrical and Electronics Engineers, 2016, pp. 221-228. ISBN 978-1-5090-0733-2.
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  MRÁZEK Vojtěch, SARWAR Syed Shakib, SEKANINA Lukáš, VAŠÍČEK Zdeněk and ROY Kaushik. Design of Power-Efficient Approximate Multipliers for Approximate Artificial Neural Networks. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Austin, TX: Association for Computing Machinery, 2016, pp. 811-817. ISBN 978-1-4503-4466-1.
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  MRÁZEK Vojtěch. Evoluční snižování příkonu: Od obvodů na úrovni tranzistorů po neuronové sítě na čipu. In: Počítačové architektury a diagnostika PAD 2016. Bořetice: Faculty of Information Technology BUT, 2016, pp. 61-64. ISBN 978-80-214-5376-0.
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  NEVORAL Jan, RŮŽIČKA Richard and MRÁZEK Vojtěch. Evolutionary Design of Polymorphic Gates Using Ambipolar Transistors. In: 2016 IEEE Symposium Series on Computational Intelligence. Athens: Institute of Electrical and Electronics Engineers, 2016, pp. 1-8. ISBN 978-1-5090-4240-1.
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  VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Evolutionary Functional Approximation of Circuits Implemented into FPGAs. In: 2016 IEEE Symposium Series on Computational Intelligence. Athens: Institute of Electrical and Electronics Engineers, 2016, pp. 1-8. ISBN 978-1-5090-4240-1.
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• 2015

  MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. In: Proceedings of 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing. Porto: Institute of Electrical and Electronics Engineers, 2015, pp. 106-113. ISBN 978-1-4673-8299-1.
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  MRÁZEK Vojtěch. Evoluční návrh nízkopříkonových obvodů. In: Počítačové architektury a diagnostika PAD 2015. Zlín: Faculty of Applied Informatics, Tomas Bata University in Zlín, 2015, pp. 1-6. ISBN 978-80-7454-522-1.
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  MRÁZEK Vojtěch, VAŠÍČEK Zdeněk and SEKANINA Lukáš. Evolutionary Approximation of Software for Embedded Systems: Median Function. In: GECCO Companion '15 Proceedings of the Companion Publication of the 2015 on Genetic and Evolutionary Computation Conference. ACM. New York: Association for Computing Machinery, 2015, pp. 795-801. ISBN 978-1-4503-3488-4.
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  MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Evolutionary Design of Transistor Level Digital Circuits using Discrete Simulation. In: Genetic Programming, 18th European Conference, EuroGP 2015. LCNS 9025. Berlin: Springer International Publishing, 2015, pp. 66-77. ISBN 978-3-319-16500-4.
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• 2014

  MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform. In: 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014, pp. 9-16. ISBN 978-1-4799-4480-4.
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  MRÁZEK Vojtěch. Akcelerace evolučního návrhu digitálních obvodů na úrovni tranzistorů s využitím platformy Zynq. In: Proceedings of the 20th Student Conference, EEICT 2014. Volume 2. Brno: Brno University of Technology, 2014, pp. 229-231. ISBN 978-80-214-4923-7.
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