Zdeněk Vašíček

Publications

• 2024

  VAŠÍČEK Zdeněk. Automated Synthesis of Commutative Approximate Arithmetic Operators. In: 2024 IEEE Congress on Evolutionary Computation, CEC 2024 - Proceedings. Yokohama: IEEE Computer Society, 2024, pp. 1-8. ISBN 979-8-3503-0836-5.
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  VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. In: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE). Valencia: Institute of Electrical and Electronics Engineers, 2024, pp. 1-6. ISBN 979-8-3503-4859-0.
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  MRÁZEK Vojtěch, KOKKINIS Argyrios, PAPANIKOLAOU Panagiotis, VAŠÍČEK Zdeněk, SIOZIOS Kostas, TZIMPRAGOS Georgios, TAHOORI Mehdi and ZERVAKIS Georgios. Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks. In: 2024 IEEE/ACM International Conference on Computer Aided Design (ICCAD). New Jersey, 2024, p. 9.
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  KLHŮFEK Jan, ŠAFÁŘ Miroslav, MRÁZEK Vojtěch, VAŠÍČEK Zdeněk and SEKANINA Lukáš. Exploiting Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. In: 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS). Kielce: Institute of Electrical and Electronics Engineers, 2024, pp. 1-6. ISBN 979-8-3503-5934-3.
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• 2023

  PIŇOS Michal, MRÁZEK Vojtěch, VAVERKA Filip, VAŠÍČEK Zdeněk and SEKANINA Lukáš. Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 13, no. 1, 2023, pp. 212-224. ISSN 2156-3357.
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  KALKREUTH Roman, VAŠÍČEK Zdeněk, HUSA Jakub, VERMETTEN Diederick, YE Furong and THOMAS Bäck. General Boolean Function Benchmark Suite. In: FOGA 2023 - Proceedings of the 17th ACM/SIGEVO Conference on Foundations of Genetic Algorithms. Potsdam: Association for Computing Machinery, 2023, pp. 84-95. ISBN 979-8-4007-0202-0.
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  GIACOBINI Mario, PAPPA Gisele and VAŠÍČEK Zdeněk, ed. Genetic Programming. LNCS 13986. Cham: Springer Verlag, 2023. ISBN 978-3-031-29572-0.
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  KALKREUTH Roman, VAŠÍČEK Zdeněk, HUSA Jakub, VERMETTEN Diederick, YE Furong and THOMAS Bäck. Towards a General Boolean Function Benchmark Suite. In: GECCO 2023 Companion - Proceedings of the 2023 Genetic and Evolutionary Computation Conference Companion. New York: Association for Computing Machinery, 2023, pp. 591-594. ISBN 979-8-4007-0120-7.
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  PRABAKARAN Bharath S., MRÁZEK Vojtěch, VAŠÍČEK Zdeněk, SEKANINA Lukáš and SHAFIQUE Muhammad. Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. In: 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD). San Francisco: Institute of Electrical and Electronics Engineers, 2023, pp. 1-9. ISBN 979-8-3503-1559-2.
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• 2022

  VAŠÍČEK Zdeněk. Analýza technického provedení a uplatnitelnosti technologie Angle of Arrival. Brno: ADWITECH system s.r.o., 2022.
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  KOCNOVÁ Jitka and VAŠÍČEK Zdeněk. Delay-aware evolutionary optimization of digital circuits. In: Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI. Nicosia, Cyprus: IEEE Computer Society, 2022, pp. 188-193. ISBN 978-1-6654-6605-9.
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  BOSIO Alberto, DI Carlo Stefano, GIRARD Patrick, RUOSPO Annachiara, SANCHEZ Ernesto, SAVINO Aessandro, SEKANINA Lukáš, TRAIOLA Marcello, VAŠÍČEK Zdeněk and VIRAZEL Arnaud. Design, Verification, Test, and In-Field Implications of Approximate Digital Integrated Circuits. Approximate Computing Techniques. Cham: Springer International Publishing, 2022, pp. 349-385. ISBN 978-3-030-94704-0.
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  KALKREUTH Roman, DAL Piccol Sotto Léo Françoso and VAŠÍČEK Zdeněk. Graph-based Genetic Programming. In: GECCO 2022 Companion - Proceedings of the 2022 Genetic and Evolutionary Computation Conference. Boston: Association for Computing Machinery, 2022, pp. 958-982. ISBN 978-1-4503-9268-6.
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  SEKANINA Lukáš, VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Inexact Arithmetic Operators. Approximate Computing Techniques. Cham: Springer International Publishing, 2022, pp. 81-107. ISBN 978-3-030-94704-0.
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  ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. SagTree: Towards Efficient Mutation in Evolutionary Circuit Approximation. Swarm and Evolutionary Computation, vol. 69, no. 100986, 2022, pp. 1-10. ISSN 2210-6502.
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• 2021

  KOCNOVÁ Jitka and VAŠÍČEK Zdeněk. Resynthesis of logic circuits using machine learning and reconvergent paths. In: 2021 24th Euromicro Conference on Digital System Design (DSD). Palermo: Institute of Electrical and Electronics Engineers, 2021, pp. 69-76. ISBN 978-1-6654-2704-3.
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  HODAŇ David, MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. Genetic Programming and Evolvable Machines, vol. 22, no. 4, 2021, pp. 539-572. ISSN 1389-2576.
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  VAŠÍČEK Zdeněk. Synthesis of approximate circuits for LUT-based FPGAs. In: 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Vienna: IEEE Computer Society, 2021, pp. 17-22. ISBN 978-1-6654-3595-6.
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• 2020

  ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. Applied Soft Computing, vol. 95, no. 106466, 2020, pp. 1-17. ISSN 1568-4946.
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  PRABAKARAN Bharath S., MRÁZEK Vojtěch, VAŠÍČEK Zdeněk, SEKANINA Lukáš and SHAFIQUE Muhammad. ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems. In: 2020 57th ACM/IEEE Design Automation Conference (DAC). San Francisco: Institute of Electrical and Electronics Engineers, 2020, pp. 1-6. ISBN 978-1-4503-6725-7.
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  BOSIO Alberto, DI Carlo Stefano, GIRARD Patrick, SANCHEZ Ernesto, SAVINO Aessandro, SEKANINA Lukáš, TRAIOLA Marcello, VAŠÍČEK Zdeněk and VIRAZEL Arnaud. Design, Verification, Test and In-Field Implications of Approximate Computing Systems. In: 25th IEEE European Test Symposium. Los Alamitos: Institute of Electrical and Electronics Engineers, 2020, pp. 1-10. ISBN 978-1-7281-4312-5.
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  KOCNOVÁ Jitka and VAŠÍČEK Zdeněk. EA-based Resynthesis: An Efficient Tool for Optimization of Digital Circuits. Genetic Programming and Evolvable Machines, vol. 21, no. 3, 2020, pp. 287-319. ISSN 1389-2576.
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  ANSARI Mohammad S., MRÁZEK Vojtěch, COCKBURN Bruce F., SEKANINA Lukáš, VAŠÍČEK Zdeněk and HAN Jie. Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 2, 2020, pp. 317-328. ISSN 1063-8210.
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  MRÁZEK Vojtěch, SEKANINA Lukáš and VAŠÍČEK Zdeněk. Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 10, no. 4, 2020, pp. 406-418. ISSN 2156-3357.
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  HODAŇ David, MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Semantically-Oriented Mutation Operator in Cartesian Genetic Programming for Evolutionary Circuit Design. In: GECCO 2020 - Proceedings of the 2020 Genetic and Evolutionary Computation Conference. Cancún: Association for Computing Machinery, 2020, pp. 940-948. ISBN 978-1-4503-7128-5.
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  VAVERKA Filip, MRÁZEK Vojtěch, VAŠÍČEK Zdeněk and SEKANINA Lukáš. TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). Grenoble: Institute of Electrical and Electronics Engineers, 2020, pp. 294-297. ISBN 978-3-9819263-4-7.
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  MRÁZEK Vojtěch, SEKANINA Lukáš and VAŠÍČEK Zdeněk. Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. In: 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems. Genoa: Institute of Electrical and Electronics Engineers, 2020, pp. 243-247. ISBN 978-1-7281-4922-6.
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• 2019

  MRÁZEK Vojtěch, VAŠÍČEK Zdeněk, SEKANINA Lukáš, HANIF Muhammad A. and SHAFIQUE Muhammad. ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Denver: Institute of Electrical and Electronics Engineers, 2019, pp. 1-8. ISBN 978-1-7281-2350-9.
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  MRÁZEK Vojtěch, HANIF Muhammad A., VAŠÍČEK Zdeněk, SEKANINA Lukáš and SHAFIQUE Muhammad. autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. In: The 56th Annual Design Automation Conference 2019 (DAC '19). Las Vegas: Association for Computing Machinery, 2019, pp. 1-6. ISBN 978-1-4503-6725-7.
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  VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Automated Circuit Approximation Method Driven by Data Distribution. In: Design, Automation and Test in Europe Conference. Florence: European Design and Automation Association, 2019, pp. 96-101. ISBN 978-3-9819263-2-3.
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  SEKANINA Lukáš, VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Automated Search-Based Functional Approximation for Digital Circuits. Approximate Circuits - Methodologies and CAD. Heidelberg: Springer International Publishing, 2019, pp. 175-203. ISBN 978-3-319-99322-5.
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  KOCNOVÁ Jitka and VAŠÍČEK Zdeněk. EA-based refactoring of mapped logic circuits. In: 2019 IEEE International Symposium on Circuits and Systems (ISCAS). Red Hook, NY: IEEE Computer Society Press, 2019, pp. 1-5. ISBN 978-1-7281-0397-6.
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  VAŠÍČEK Zdeněk. Formal Methods for Exact Analysis of Approximate Circuits. IEEE Access, vol. 7, no. 1, 2019, pp. 177309-177331. ISSN 2169-3536.
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  KOCNOVÁ Jitka and VAŠÍČEK Zdeněk. Impact of subcircuit selection on the efficiency of CGP-based optimization of gate-level circuits. In: GECCO '19 Proceedings of the Genetic and Evolutionary Computation Conference Companion. New York: Association for Computing Machinery, 2019, pp. 377-378. ISBN 978-1-4503-6748-6.
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  KOCNOVÁ Jitka and VAŠÍČEK Zdeněk. Towards a Scalable EA-based Optimization of Digital Circuits. In: Genetic Programming 22nd European Conference, EuroGP 2019. Cham: Springer International Publishing, 2019, pp. 81-97. ISBN 978-3-030-16669-4.
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• 2018

  ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. ADAC: Automated Design of Approximate Circuits. In: Proceedings of 30th International Conference on Computer Aided Verification (CAV'18). Oxford, UK: Springer International Publishing, 2018, pp. 612-620. ISBN 978-3-319-96145-3.
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  VAŠÍČEK Zdeněk. Bridging the Gap Between Evolvable Hardware and Industry Using Cartesian Genetic Programming. Inspired by Nature. Emergence, Complexity and Computation, Vol. 28. Cham: Springer International Publishing, 2018, pp. 39-55. ISBN 978-3-319-67996-9.
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  MRÁZEK Vojtěch, VAŠÍČEK Zdeněk and SEKANINA Lukáš. Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. In: Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems. Edinburgh: Institute of Electrical and Electronics Engineers, 2018, pp. 264-271. ISBN 978-1-5386-7753-7.
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  SEKANINA Lukáš, MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. In: 25th IEEE International Conference on Electronics Circuits and Systems (ICECS). Bordeaux: IEEE Circuits and Systems Society, 2018, pp. 377-380. ISBN 978-1-5386-9562-3.
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  MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Evolutionary Design of Large Approximate Adders Optimized for Various Error Criteria. In: Proceedings of the Genetic and Evolutionary Computation Conference Companion (GECCO '18). Kyoto: Association for Computing Machinery, 2018, pp. 294-295. ISBN 978-1-4503-5764-7.
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  MRÁZEK Vojtěch, SÝS Marek, VAŠÍČEK Zdeněk, SEKANINA Lukáš and MATYÁŠ Václav. Evolving Boolean Functions for Fast and Efficient Randomness Testing. In: Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '18). Kyoto: Association for Computing Machinery, 2018, pp. 1302-1309. ISBN 978-1-4503-5618-3.
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  MRÁZEK Vojtěch, VAŠÍČEK Zdeněk and HRBÁČEK Radek. Role of circuit representation in evolutionary design of energy-efficient approximate circuits. IET Computers & Digital Techniques, vol. 2018, no. 4, pp. 139-149. ISSN 1751-8601.
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  MRÁZEK Vojtěch, VAŠÍČEK Zdeněk, SEKANINA Lukáš, JIANG Honglan and HAN Jie. Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 11, 2018, pp. 2572-2576. ISSN 1063-8210.
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  SEKANINA Lukáš, VAŠÍČEK Zdeněk, BOSIO Alberto, TRAIOLA Marcello, RECH Paolo, OLIVEIRA Daniel, FERNANDES Fernando and DI Carlo Stefano. Special Session: How Approximate Computing impacts Verification, Test and Reliability. 2018 IEEE 36th VLSI Test Symposium. San Francisco: IEEE Computer Society, 2018. ISBN 978-1-5386-3774-6.
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• 2017

  SHAFIQUE Muhammad, HAFIZ Rehan, JAVED Muhammad Usama, ABBAS Sarmad, SEKANINA Lukáš, VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. In: 2017 IEEE Computer Society Annual Symposium on VLSI. Los Alamitos: IEEE Computer Society Press, 2017, pp. 627-632. ISBN 978-1-5090-6762-6.
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  SEKANINA Lukáš, VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Approximate Circuits in Low-Power Image and Video Processing: The Approximate Median Filter. Radioengineering, vol. 26, no. 3, 2017, pp. 623-632. ISSN 1210-2512.
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  ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished. In: Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD). Irvine, CA: Institute of Electrical and Electronics Engineers, 2017, pp. 416-423. ISBN 978-1-5386-3093-8.
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  MRÁZEK Vojtěch, HRBÁČEK Radek, VAŠÍČEK Zdeněk and SEKANINA Lukáš. EvoApprox8b: Library of Approximate Adders and Multipliers for Circuit Design and Benchmarking of Approximation Methods. In: Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017, pp. 258-261. ISBN 978-3-9815370-9-3.
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  MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Parallel Optimization of Transistor Level Circuits using Cartesian Genetic Programming. In: GECCO Companion '17 Proceedings of the Companion Publication of the 2017 on Genetic and Evolutionary Computation Conference. Berlin: Association for Computing Machinery, 2017, pp. 1849-1856. ISBN 978-1-4503-4939-0.
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  VAŠÍČEK Zdeněk. Relaxed equivalence checking: a new challenge in logic synthesis. In: Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems. Dresden: IEEE Computer Society, 2017, pp. 1-6. ISBN 978-1-5386-0472-4.
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  VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Towards Low Power Approximate DCT Architecture for HEVC Standard. In: Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017, pp. 1576-1581. ISBN 978-3-9815370-9-3.
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  VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Trading between Quality and Non-functional Properties of Median Filter in Embedded Systems. Genetic Programming and Evolvable Machines, vol. 18, no. 1, 2017, pp. 45-82. ISSN 1389-2576.
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• 2016

  HRBÁČEK Radek, MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Automatic Design of Approximate Circuits by Means of Multi-Objective Evolutionary Algorithms. In: Proceedings of the 11th International Conference on Design & Technology of Integrated Systems in Nanoscale Era. Istanbul: Istanbul Sehir University, 2016, pp. 239-244. ISBN 978-1-5090-0335-8.
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  MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Automatic Design of Arbitrary-Size Approximate Sorting Networks with Error Guarantee. In: Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016 26rd International Workshop on. Bremen: Institute of Electrical and Electronics Engineers, 2016, pp. 221-228. ISBN 978-1-5090-0733-2.
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  MRÁZEK Vojtěch, SARWAR Syed Shakib, SEKANINA Lukáš, VAŠÍČEK Zdeněk and ROY Kaushik. Design of Power-Efficient Approximate Multipliers for Approximate Artificial Neural Networks. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Austin, TX: Association for Computing Machinery, 2016, pp. 811-817. ISBN 978-1-4503-4466-1.
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  VAŠÍČEK Zdeněk and SEKANINA Lukáš. Evolutionary Design of Complex Approximate Combinational Circuits. Genetic Programming and Evolvable Machines, vol. 17, no. 2, 2016, pp. 169-192. ISSN 1389-2576.
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  VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Evolutionary Functional Approximation of Circuits Implemented into FPGAs. In: 2016 IEEE Symposium Series on Computational Intelligence. Athens: Institute of Electrical and Electronics Engineers, 2016, pp. 1-8. ISBN 978-1-5090-4240-1.
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  SEKANINA Lukáš and VAŠÍČEK Zdeněk. Genetic Improvement for Approximate Computing. In: 2nd Workshop on Approximate Computing (WAPCO 2016). Prague, 2016, pp. 1-2.
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  VAŠÍČEK Zdeněk. New Methods for Synthesis and Approximation of Logic Circuits. Brno, 2016.
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  VAŠÍČEK Zdeněk and SEKANINA Lukáš. Search-based synthesis of approximate circuits implemented into FPGAs. In: 26th International Conference on Field Programmable Logic and Applications. Lausanne: Institute of Electrical and Electronics Engineers, 2016, pp. 1-4. ISBN 978-2-8399-1844-2.
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  HOLÍK Lukáš, LENGÁL Ondřej, ROGALEWICZ Adam, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. Towards Formal Relaxed Equivalence Checking in Approximate Computing Methodology. In: 2nd Workshop on Approximate Computing (WAPCO 2016). Prague, 2016, pp. 1-6.
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• 2015

  MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. In: Proceedings of 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing. Porto: Institute of Electrical and Electronics Engineers, 2015, pp. 106-113. ISBN 978-1-4673-8299-1.
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  VAŠÍČEK Zdeněk. Cartesian GP in Optimization of Combinational Circuits with Hundreds of Inputs and Thousands of Gates. In: Genetic Programming, 18th European Conference, EuroGP 2015. LCNS 9025. Berlin: Springer International Publishing, 2015, pp. 139-150. ISBN 978-3-319-16500-4.
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  VAŠÍČEK Zdeněk and SEKANINA Lukáš. Circuit Approximation Using Single- and Multi-Objective Cartesian GP. In: Genetic Programming. Lecture Notes in Computer Science, vol. 9025. Berlin: Springer International Publishing, 2015, pp. 217-229. ISBN 978-3-319-16500-4.
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  VAŠÍČEK Zdeněk and SEKANINA Lukáš. Evolutionary Approach to Approximate Digital Circuits Design. IEEE Transactions on Evolutionary Computation, vol. 19, no. 3, 2015, pp. 432-444. ISSN 1089-778X.
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  VAŠÍČEK Zdeněk and SEKANINA Lukáš. Evolutionary approximation of complex digital circuits. In: Proceedings of the Companion Publication of the 2015 on Genetic and Evolutionary Computation Conference. New York: Association for Computing Machinery, 2015, pp. 1505-1506. ISBN 978-1-4503-3488-4.
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  MRÁZEK Vojtěch, VAŠÍČEK Zdeněk and SEKANINA Lukáš. Evolutionary Approximation of Software for Embedded Systems: Median Function. In: GECCO Companion '15 Proceedings of the Companion Publication of the 2015 on Genetic and Evolutionary Computation Conference. ACM. New York: Association for Computing Machinery, 2015, pp. 795-801. ISBN 978-1-4503-3488-4.
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  SEKANINA Lukáš and VAŠÍČEK Zdeněk. Evolutionary Computing in Approximate Circuit Design and Optimization. In: 1st Workshop on Approximate Computing (WAPCO 2015). Amsterdam, 2015, pp. 1-6.
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  MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Evolutionary Design of Transistor Level Digital Circuits using Discrete Simulation. In: Genetic Programming, 18th European Conference, EuroGP 2015. LCNS 9025. Berlin: Springer International Publishing, 2015, pp. 66-77. ISBN 978-3-319-16500-4.
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  SEKANINA Lukáš and VAŠÍČEK Zdeněk. Functional Equivalence Checking for Evolution of Complex Digital Circuits. Evolvable Hardware - From Practice to Application. Berlin: Springer Verlag, 2015, pp. 175-189. ISBN 978-3-662-44615-7.
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• 2014

  MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform. In: 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014, pp. 9-16. ISBN 978-1-4799-4480-4.
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  SEKANINA Lukáš, PTÁK Ondřej and VAŠÍČEK Zdeněk. Cartesian Genetic Programming as Local Optimizer of Logic Networks. In: 2014 IEEE Congress on Evolutionary Computation. Beijing: IEEE Computational Intelligence Society, 2014, pp. 2901-2908. ISBN 978-1-4799-1488-3.
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  VAŠÍČEK Zdeněk and SEKANINA Lukáš. Evolutionary Design of Approximate Multipliers Under Different Error Metrics. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warsaw: IEEE Computer Society, 2014, pp. 135-140. ISBN 978-1-4799-4558-0.
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  VAŠÍČEK Zdeněk and SEKANINA Lukáš. How to Evolve Complex Combinational Circuits From Scratch?. In: 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014, pp. 133-140. ISBN 978-1-4799-4480-4.
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  BIDLO Michal and VAŠÍČEK Zdeněk. On Evolution of Multi-Category Pattern Classifiers Suitable for Embedded Systems. In: Genetic Programming, 17th European Conference, EuroGP 2014. Lecture Notes in Computer Science, vol. 8599. Berlin: Springer Verlag, 2014, pp. 234-245. ISBN 978-3-662-44302-6.
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  SEKANINA Lukáš and VAŠÍČEK Zdeněk. On Evolutionary Approximation of Logic Circuits. Computing with New Resources. Berlin: Springer Verlag, 2014, pp. 367-378. ISBN 978-3-319-13349-2.
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• 2013

  SEKANINA Lukáš and VAŠÍČEK Zdeněk. Approximate Circuit Design by Means of Evolvable Hardware. In: 2013 IEEE International Conference on Evolvable Systems (ICES). Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI). Singapur: IEEE Computer Society, 2013, pp. 21-28. ISBN 978-1-4673-5847-7.
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  BIDLO Michal and VAŠÍČEK Zdeněk. Evolution of Cellular Automata with Conditionally Matching Rules. In: 2013 IEEE Congress on Evolutionary Computation (CEC 2013). Cancún: IEEE Computer Society, 2013, pp. 1178-1185. ISBN 978-1-4799-0452-5.
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  VAŠÍČEK Zdeněk, BIDLO Michal and SEKANINA Lukáš. Evolution of efficient real-time non-linear image filters for FPGAs. Soft Computing, vol. 17, no. 11, 2013, pp. 2163-2180. ISSN 1432-7643.
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  BIDLO Michal and VAŠÍČEK Zdeněk. Functional-Level Development of Image Filters by Means of Cellular Automata. In: 2013 IEEE International Conference on Evolvable Systems (ICES). Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI). Singapore: IEEE Computer Society, 2013, pp. 29-36. ISBN 978-1-4673-5847-7.
  Detail

  SEKANINA Lukáš, RŮŽIČKA Richard, VAŠÍČEK Zdeněk, ŠIMEK Václav and HANÁČEK Petr. Implementing a Unique Chip ID on a Reconfigurable Polymorphic Circuit. Information Technology And Control, vol. 42, no. 1, 2013, pp. 7-14. ISSN 1392-124X.
  Detail

• 2012

  SEKANINA Lukáš and VAŠÍČEK Zdeněk. A SAT-based Fitness Function for Evolutionary Optimization of Polymorphic Circuits. In: Proc. of the 2012 Design, Automation and Test in Europe. Dresden: European Design and Automation Association, 2012, pp. 715-720. ISBN 978-1-4577-2145-8.
  Detail

  BIDLO Michal and VAŠÍČEK Zdeněk. Cellular Automaton as a Sorting Network Generator Using Instruction-Based Development. Lecture Notes in Computer Science, vol. 2012, no. 7495, pp. 214-223. ISSN 0302-9743.
  Detail

  VAŠÍČEK Zdeněk and SLANÝ Karel. Efficient Phenotype Evaluation in Cartesian Genetic Programming. In: Proc. of the 15th European Conference on Genetic Programming. Lecture Notes in Computer Science, vol. 7244. Heidelberg: Springer Verlag, 2012, pp. 266-278. ISBN 978-3-642-29138-8.
  Detail

  BIDLO Michal and VAŠÍČEK Zdeněk. Evolution of Cellular Automata Using Instruction-Based Approach. In: 2012 IEEE World Congress on Computational Intelligence. CA: Institute of Electrical and Electronics Engineers, 2012, pp. 1060-1067. ISBN 978-1-4673-1508-1.
  Detail

  VAŠÍČEK Zdeněk and SEKANINA Lukáš. On Area Minimization of Complex Combinational Circuits Using Cartesian Genetic Programming. In: 2012 IEEE World Congress on Computational Intelligence. CA: Institute of Electrical and Electronics Engineers, 2012, pp. 2379-2386. ISBN 978-1-4673-1508-1.
  Detail

  SEKANINA Lukáš, SALAJKA Vojtěch and VAŠÍČEK Zdeněk. Two-Step Evolution of Polymorphic Circuits for Image Multi-Filtering. In: 2012 IEEE World Congress on Computational Intelligence. CA: Institute of Electrical and Electronics Engineers, 2012, pp. 432-439. ISBN 978-1-4673-1508-1.
  Detail

• 2011

  VAŠÍČEK Zdeněk and SEKANINA Lukáš. A Global Postsynthesis Optimization Method for Combinational Circuits. In: Proc. of the Design, Automation and Test in Europe DATE 2011. Grenoble: European Design and Automation Association, 2011, pp. 1525-1528. ISBN 978-3-9810801-7-9.
  Detail

  SEKANINA Lukáš and VAŠÍČEK Zdeněk. CGP Acceleration Using Field-Programmable Gate Arrays. Cartesian Genetic Programming. Natural Computing Series. Berlin: Springer Verlag, 2011, pp. 217-230. ISBN 978-3-642-17309-7.
  Detail

  VAŠÍČEK Zdeněk, BIDLO Michal, SEKANINA Lukáš and GLETTE Kyrre. Evolutionary Design of Efficient and Robust Switching Image Filters. In: Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2011, pp. 192-199. ISBN 978-1-4577-0599-1.
  Detail

  VAŠÍČEK Zdeněk and BIDLO Michal. Evolutionary Design of Robust Noise-Specific Image Filters. In: 2011 IEEE Congress on Evolutionary Computation. New Orleans: IEEE Computer Society, 2011, pp. 269-276. ISBN 978-1-4244-7834-7.
  Detail

  VAŠÍČEK Zdeněk and SEKANINA Lukáš. Evolutionary Optimization of Complex Digital Circuits. In: 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2011, p. 1. ISBN 978-80-214-4305-1.
  Detail

  VAŠÍČEK Zdeněk and SEKANINA Lukáš. Extensions of Cartesian Genetic Programming for Optimization of Complex Combinational Circuits. In: Proc. of the 20th International Workshop on Logic and Synthesis. San Diego: University of California San Diego, 2011, pp. 55-61.
  Detail

  VAŠÍČEK Zdeněk and SEKANINA Lukáš. Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. Genetic Programming and Evolvable Machines, vol. 12, no. 3, 2011, pp. 305-327. ISSN 1389-2576.
  Detail

  JIRÁK Ota, KŘIVKA Zbyněk and VAŠÍČEK Zdeněk. Integrated Development Environment for Virtual Laboratory. In: International Technology, Education and Development Conference. Valencia: International Association for Technology, Education and Development, 2011, p. 10. ISBN 978-84-614-7423-3.
  Detail

  KŘIVKA Zbyněk and VAŠÍČEK Zdeněk. The Virtualization of Development Boards in the Virtual Laboratory of Microprocessor Technology. In: 12th International Carpathian Control Conference (ICCC). Velké Karlovice: VŠB-Technical University of Ostrava, 2011, pp. 424-428. ISBN 978-1-61284-359-9.
  Detail

  DULÍK Tomáš, KŘIVKA Zbyněk, KADLEC Jiří, BLIŽŇÁK Michal, BUDÍKOVÁ Věra, JIRÁK Ota, OLŠAROVÁ Nela, TRBUŠEK Josef and VAŠÍČEK Zdeněk. Virtuální laboratoř pro vývoj aplikací s mikroprocesory a FPGA. Brno: Akademické nakladatelství CERM, 2011. ISBN 978-80-7204-754-3.
  Detail

• 2010

  VAŠÍČEK Zdeněk, SEKANINA Lukáš and BIDLO Michal. A Method for Design of Impulse Bursts Noise Filters Optimized for FPGA Implementations. In: DATE 2010: Design, Automation and Test in Europe. Dresden: European Design and Automation Association, 2010, pp. 1731-1736. ISBN 978-3-9810801-6-2.
  Detail

  JIRÁK Ota, KŘIVKA Zbyněk and VAŠÍČEK Zdeněk. Component Interconnection Inference Tool Supporting the Design of Small FPGA-based Embedded Systems. In: Proceedings of the IADIS International Conference Applied Computing 2010. Timisoara: International Association for Development of the Information Society, 2010, pp. 230-234. ISBN 978-972-8939-30-4.
  Detail

  VAŠÍČEK Zdeněk and SEKANINA Lukáš. Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units. Computing and Informatics, vol. 29, no. 6, 2010, pp. 1359-1371. ISSN 1335-9150.
  Detail

  JIRÁK Ota, KŘIVKA Zbyněk, OLŠAROVÁ Nela and VAŠÍČEK Zdeněk. Odvozování propojení komponent pro podporu návrhu pro malé FPGA čipy. In: DATAKON 2010 Proceedings (Ed. Petr Šaloun). Mikulov: University of Ostrava, 2010, pp. 81-90. ISBN 978-80-7368-424-2.
  Detail

  FIŠER Petr, SCHMIDT Jan, VAŠÍČEK Zdeněk and SEKANINA Lukáš. On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming. In: Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010, pp. 346-351. ISBN 978-1-4244-6610-8.
  Detail

  BIDLO Michal, SLANÝ Karel and VAŠÍČEK Zdeněk. Sorting Network Development Using Cellular Automata. In: Evolvable Systems: From Biology to Hardware. 9th International Conference, ICES 2010, York, UK, September 6-8, 2010, Proceedings, LNCS 6274. London: Springer London, 2010, pp. 85-96. ISBN 978-3-642-15322-8.
  Detail

  VAŠÍČEK Zdeněk. Využití a akcelerace evolučních technik pro návrh číslicových obvodů. In: Počítačové architektury a diagnostika 2010. Brno: Faculty of Information Technology BUT, 2010, pp. 165-170. ISBN 978-80-214-4140-8.
  Detail

• 2009

  BIDLO Michal and VAŠÍČEK Zdeněk. Comparison of the Uniform and Non-Uniform Cellular Automata-Based Approach to the Development of Combinational Circuits. In: Proceedings 2009 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2009, pp. 423-430. ISBN 978-0-7695-3714-6.
  Detail

  BIDLO Michal and VAŠÍČEK Zdeněk. Development of Combinational Circuits Using Non-Uniform Cellular Automata: Initial Results. In: Genetic and Evolutionary Computation. New York: Association for Computing Machinery, 2009, pp. 1839-1840. ISBN 978-1-60558-325-9.
  Detail

  VAŠÍČEK Zdeněk and SEKANINA Lukáš. Efficient Hardware Accelerator for Symbolic Regression Problems. In: 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2009, pp. 192-199. ISBN 978-80-87342-04-6.
  Detail

  SEKANINA Lukáš, VAŠÍČEK Zdeněk, RŮŽIČKA Richard, BIDLO Michal, JAROŠ Jiří and ŠVENDA Petr. Evoluční hardware: Od automatického generování patentovatelných invencí k sebemodifikujícím se strojům. Edice Gerstner. Praha: Academia, 2009. ISBN 978-80-200-1729-1.
  Detail

  VAŠÍČEK Zdeněk, BIDLO Michal, SEKANINA Lukáš, TORRESEN Jim, GLETTE Kyrre and FURUHOLMEN Marcus. Evolution of Impulse Bursts Noise Filters. In: Proc. of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2009, pp. 27-34. ISBN 978-0-7695-3714-6.
  Detail

  BIDLO Michal and VAŠÍČEK Zdeněk. Investigating Gate-Level Evolutionary Development of Combinational Multipliers Using Enhanced Cellular Automata-Based Model. In: Proc. of 2009 IEEE Congress on Evolutionary Computation. NA: IEEE Computational Intelligence Society, 2009, pp. 2241-2248. ISBN 978-1-4244-2958-5.
  Detail

  SEKANINA Lukáš, RŮŽIČKA Richard, VAŠÍČEK Zdeněk, PROKOP Roman and FUJCIK Lukáš. REPOMO32 - New Reconfigurable Polymorphic Integrated Circuit for Adaptive Hardware. In: Proc. of the 2009 IEEE Symposium Series on Computational Intelligence - Workshop on Evolvable and Adaptive Hardware. Nashville: IEEE Computational Intelligence Society, 2009, pp. 39-46. ISBN 978-1-4244-2755-0.
  Detail

• 2008

  VAŠÍČEK Zdeněk. Adaptivní hardware na bázi vyvíjejících se obvodů. In: Počítačové architektury a diagnostika 2008. Česko-slovenský seminář pro studenty doktorandského studia. Liberec: Liberec University of Technology, 2008, pp. 119-124. ISBN 978-80-7372-378-1.
  Detail

  VAŠÍČEK Zdeněk, ČAPKA Ladislav and SEKANINA Lukáš. Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit. In: Proc. of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2008, pp. 3-10. ISBN 978-0-7695-3166-3.
  Detail

  ŠIMEK Václav, VAŠÍČEK Zdeněk and SLANÝ Karel. Can the performance of GPGPU really beat CPU in evolutionary design task?. In: 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2008, pp. 264-264. ISBN 978-80-7355-082-0.
  Detail

  BIDLO Michal and VAŠÍČEK Zdeněk. Cellular Automata-Based Development of Combinational and Polymorphic Circuits: A Comparative Study. In: Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science, vol. 5216. Berlin: Springer Verlag, 2008, pp. 106-117. ISBN 978-3-540-85856-0.
  Detail

  JIRÁK Ota, KŘIVKA Zbyněk and VAŠÍČEK Zdeněk. Debugging of Small FPGA-Based Embedded System. In: Proceedings of ASIS 2008. Ostrava, 2008, p. 6. ISBN 978-80-86840-42-0.
  Detail

  BIDLO Michal and VAŠÍČEK Zdeněk. Gate-Level Evolutionary Development Using Cellular Automata. In: 2008 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society Press, 2008, pp. 11-18. ISBN 978-0-7695-3166-3.
  Detail

  VAŠÍČEK Zdeněk and SEKANINA Lukáš. Hardware Accelerators for Cartesian Genetic Programming. In: Eleventh European Conference on Genetic Programming. Lecture Notes in Computer Science, vol. 4971. Berlin: Springer Verlag, 2008, pp. 230-241. ISBN 978-3-540-78670-2.
  Detail

  VAŠÍČEK Zdeněk and SEKANINA Lukáš. Novel Hardware Implementation of Adaptive Median Filters. In: Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008, pp. 110-115. ISBN 978-1-4244-2276-0.
  Detail

  VAŠÍČEK Zdeněk, ŽÁDNÍK Martin, SEKANINA Lukáš and TOBOLA Jiří. On Evolutionary Synthesis of Linear Transforms. In: Evolvable Systems: From Biology > to > Hardware. Lecture Notes in Computer Science, vol. 5216. Berlin: Springer Verlag, 2008, pp. 141-152. ISBN 978-3-540-85856-0.
  Detail

  VAŠÍČEK Zdeněk. Towards Automatic Design of Competitive Image Filters in FPGAs. In: Proceedings of Junior Scientist Conference 2008. Vienna: Technical University Wien, 2008, p. 2. ISBN 978-3-200-01612-5.
  Detail

• 2007

  VAŠÍČEK Zdeněk and SEKANINA Lukáš. An Area-Efficient Alternative to Adaptive Median Filtering in FPGAs. In: Proc. of 2007 International Conference on Field Programmable Logic and Applications. Los Alamitos: IEEE Computer Society, 2007, pp. 216-221. ISBN 1424410606.
  Detail

  VAŠÍČEK Zdeněk and SEKANINA Lukáš. An Evolvable Hardware System in Xilinx Virtex II Pro FPGA. International Journal of Innovative Computing and Applications, vol. 1, no. 1, 2007, pp. 63-73. ISSN 1751-648X.
  Detail

  VAŠÍČEK Zdeněk and SEKANINA Lukáš. Evaluation of a New Platform For Image Filter Evolution. In: Proc. of the 2007 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2007, pp. 577-584. ISBN 076952866X.
  Detail

  DRAHANSKÝ Martin and VAŠÍČEK Zdeněk. Image stabilization in a video-stream. IDET 2007, Brno: EVPU Defence, s.r.o., 2007.
  Detail

  ČAPKA Ladislav and VAŠÍČEK Zdeněk. Investigating the Influence of Mutation Operators in Cartesian Genetic Programming. In: 13th International Conference on Soft Computing. Brno: Faculty of Mechanical Engineering BUT, 2007, pp. 43-47. ISBN 978-80-214-3473-8.
  Detail

  VAŠÍČEK Zdeněk. Reálné aplikace evolučního návrhu. In: Počítačové architektury a diagnostika 2007. Česko-slovenský seminář pro studenty doktorandského studia. Plzeň: University of West Bohemia in Pilsen, 2007, pp. 137-142. ISBN 978-80-7043-605-9.
  Detail

  VAŠÍČEK Zdeněk and SEKANINA Lukáš. Reducing the Area on a Chip Using a Bank of Evolved Filters. In: Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science, vol. 4684. Berlin: Springer Verlag, 2007, pp. 222-232. ISBN 978-3-540-74625-6.
  Detail

• 2006

  SEKANINA Lukáš and VAŠÍČEK Zdeněk. On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level. In: Applications of Evolutionary Computing. Lecture Notes in Computer Science, vol. 3907. Berlin: Springer Verlag, 2006, pp. 344-355. ISBN 978-3-540-33237-4.
  Detail

• 2004

  VAŠÍČEK Zdeněk and SEKANINA Lukáš. Evoluční návrh kombinačních obvodů. Elektrorevue - www.elektrorevue.cz, vol. 2004, no. 43, pp. 1-6. ISSN 1213-1539.
  Detail