Dependable Digital Systems Research Group
Dependable Digital Systems Research Group
The group researches methods for the design and implementation of modern digital systems with an emphasis on reliability, safety, and related features. The interests of the group members span the levels of digital circuit design and modelling from the transistor level through the gate level, RT, and up to the system level.
Research interests
- Reliability and safety
- Fault injection and fault tolerant systems
- Cyber-physical, critical, real-time and reconfigurable systems
- Functional verification and modeling checking of systems
- Assessment of dependability attributes of systems
- Novel and unconventional approaches to dependability related problems
- Design methods and techniques for digital systems in the "Beyond-CMOS" era
Current research topics
- Increasing dependability by means of partial dynamic reconfiguration in an FPGA (contact: Josef Strnadel). Keywords: partial dynamic reconfiguration, control, controller, FPGA.
- Means of a fault injection into an FPGA (contact: Josef Strnadel). Keywords: fault, injection, FPGA.
- Methods for acceleration of functional verification using machine learning algorithms (contact: Marcela Šimková). Keywords: functional verification, UVM, machine learning algorithms, acceleration, automation.
- Vertical reusability of verification models between different levels of digital circuit design (contact: Marcela Zachariášová). Keywords: portable models, PSS, functional verification, UVM.
- Dependability of critical and cyber-physical systems (contact: Josef Strnadel). Keywords: dependability, quantification of dependability attributes, processor, operating system, real time, control, formal verification, model checking.
- Unconventional and Emerging Technologies and Techniques of Digital Systems Design (contact: Richard Růžička). Keywords: polymorphic electronics, ambipolar elements.
- Protection against unauthorized modifications of digital systems in the process of their design and production (contact: Richard Růžička). Keywords: hardware trojan horses, obfuscation, watermarking, physically unclonable functions (PUF).
Significant results
- Publishing an article "Predictability Analysis of Interruptible Systems by Statistical Model Checking" in IEEE Design & Test
- Publishing an article "Functional Verification Based Platform for Evaluating Fault Tolerance Properties" in Microprocessors and Microsystems
- Software GDRC: Generic partial dynamic reconfiguration controller
- Tools enabling to develop fault tolerant architectures and checkers from VHDL
- Prototype intMAN: Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems
- Publishing a book "Hardware Accelerated Functional Verification"
Cooperation
- We welcome cooperation and offer the opportunity to engage others in our research topics (e.g., during the Ph.D. study or intership) or doing a short-term work (e.g., during the project practice, Bc. or MSc. thesis).
- We offer our institutional, industrial and other partners, e.g., the possibility of joint participation in national, European or international projects.
More information
- Typically, group members publish their papers at international conferences such as IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Euromicro Conference on Digital System Design (DSD), Design and Verification Conference (DVCON) and in journals such as Microprocessors and Microsystems or Computing and Informatics.
- For realization purposes, we use particularly field programmable gate arrays (FPGA) and development tools from Xilinx, microcontrollers (MCU) and development tools from NXP, ARM and tools from Siemens and Cadence company.
Information
Dependable Digital Systems Research Group
Brno University of Technology, Faculty of Information Technology
Božetěchova 2
612 00 Brno
Czech Republic
Tel.: +420 54114-1223
Fax.: +420 54114-1270
E-mail: kotasek@fit.vutbr.cz