Zapojení pro rychlý výpočet kontrolního součtu CRC obvodem připojeným přímo ke sběrnici pro přenos datových paketů

Cyclic Redundancy Check, CRC, high-speed, hardware architecture

The invention is a circuit for quickly calculating a CRC (Cyclic Redundancy Check) checksum by a circuit connected directly to a data packet bus. The main benefit of the proposed architecture is to efficiently calculate independent CRC values for multiple packets transmitted on the bus in parallel, i.e. in one data word or cycle of the synchronization clock signal. The connection architecture is flexible and supports the processing of general data packets of any variable length, which do not have to be aligned to bus words. The connection architecture can be used without change to calculate the CRC sums of any data width described by any generating polynomial.