Pokročilý akcelerátor zpracování radarového signálu

radar, signal processing, FPGA

It is not always necessary to execute algorithms of radar signal processing by complex processors with large instruction set. It is possible to employ dedicated processing unit with relatively low computational power but well optimized ad hoc instruction set. This way, a CPU can be completely elliminated and whole processing can be done only by a FPGA. This saves both money and energy.

In this functional sample was a soft-core Codix-RISC used. This core can be synthesized into FPGA such as the one used e.g. in the Camea AX32 platform. The Codix processor allows adding or removing instruction and as result is the computing unit very efficient. It can be also combined with other units such as IP FFT that can handle other computations.

For licence please consult: Mgr. Michaela Kavková, Research Centre of Information Technology, Faculty of Information Technology, BUT Brno, Božetěchova 2, 612 66 Brno, 541 141 470

• pdf HW accelerator for radar signal processing 338 KB