Product Details

Nástroje pro generování odolných architektur a hlídacích obvodů z jazyka VHDL

Created: 2015

English title
Tools enabling to develop fault tolerant architectures and checkers from VHDL
Type
software
License
optional - free
Authors
Straka Martin, Ing., Ph.D. (DCSY FIT BUT)
Keywords

tool, vhdl, fault tolerant architecture, checker

Description

Tools for generating different types of fault tolerant architectures from VHDL description of the components and their checkers.

Location

http://www.fit.vutbr.cz/research/grants/index.php.cs?id=618

Projects
Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification (LD12036)
Research groups
Dependable Systems Research Group (VZ DEPSYS)
Departments
Department of Computer Systems FIT BUT (DCSY FIT BUT)
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