Product Details

Set of tools for RTL circuits testability analysis

Created: 2007

Czech title
Sada nástrojů pro analýzu testovatelnosti obvodů na úrovni RTL
Type
software
License
required - free
Authors
Škarvada Jaroslav, Ing., Ph.D. (DCSY FIT BUT)
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT)
Keywords

RTL, testability analysis, I-paths search, formal model, scan chain design

Description

Homepage of the product: http://www.fit.vutbr.cz/~skarvada/ruz/
Developed tools can be used for automatic transformation of digital circuit design written in structural VHDL to formal model that was developed on DCS. It is possible to use them for transparent data paths (I-paths) search, testability analysis, scan chain design. Custom cell libraries can be used.

Location

Homepage of the product: http://www.fit.vutbr.cz/~skarvada/ruz/

Licence

This product is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version, see http://www.fsf.org/licensing/licenses/gpl.html

Projects
Security-Oriented Research in Information Technology (MSM0021630528)
Research groups
Dependable Systems Research Group (VZ DEPSYS)
Departments
Department of Computer Systems FIT BUT (DCSY FIT BUT)
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