Tools for split RTL circuit into Testable blocks

RTL, testability analysis, formal model, scan chain design, Testable block

Developed tools make possible to split circuit written in formal model that was developed on DSC into Testable blocks and design scan chain. Outputs of tools are individual Testable blocks written in verilog.

This product is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version, see http://www.fsf.org/licensing/licenses/gpl.html

• zip Circuits for testing 1782 KB
• ZIP Tools for split RTL circuit into Testable blocks 1038 KB