FAST to ARMC Translator

English title

Type

software

License

required - free

Authors

Smrčka Aleš, Ing., Ph.D. (DITS FIT BUT)

Keywords

VHDL, counter automata, translator, model, formal verification

Description

The program translates a model for FAST or for FASTer tool to ARMC model checker. The goal of the project is to achieve better experiment results of many of FAST models due to great effectiveness of ARMC (almost 7x faster then FASTer on several models). The translator completely understands a FAST/FASTer model specification and the main part of strategy description. The translator can be simply rewriten to support different output languages so the user is then able to write the model in one language (FAST) and verify it in different tools.

Location

http://fast2armc.sourceforge.net/

Licence

Free software under the terms of GNU GPL (cf. http://www.gnu.org/licenses/gpl.html).

Projects

Security-Oriented Research in Information Technology (MSM0021630528)

Research groups

Automated Analysis and Verification Research Group - VeriFIT (VZ VERIFIT)
Formal verification and simulation for the design of secure systems (DC7-VZ)

Departments

Department of Intelligent Systems FIT BUT (DITS FIT BUT)