Sondy pro analýzu a filtraci provozu na úrovni aplikačních protokolů

English title

Smart Application Aware Embedded Probes

Type

grant

Keywords

lawful interception, application protocol, probe, FPGA

Abstract

The aim of the project is to create small and flexible network probes capable of lawful interception up to the application layer, to be used by the law enforcement agencies. The concept of software defined monitoring and the FPGA SoC computation platform will be used to achieve the required performance. The probe will, besides the detailed traffic analysis and filtering, provide statistical information and the information regarding the quality of the measured data. It will also identify the encrypted traffic and adjust the data acquisition to the available hardware resources.

Team members

Kořenek Jan, doc. Ing., Ph.D. (DCSY FIT BUT) , research leader
Korček Pavol, Ing., Ph.D. (DCSY FIT BUT) , team leader
Žádník Martin, Ing., Ph.D. (DCSY FIT BUT) , team leader
Dobai Roland, Ing., Ph.D. (DCSY FIT BUT)
Košař Vlastimil, Ing., Ph.D. (DCSY FIT BUT)
Puš Viktor, Ing., Ph.D. (CESNET)
Viktorin Jan, Ing. (DCSY FIT BUT)

Publications

2020

KEKELY Michal, KEKELY Lukáš and KOŘENEK Jan. General memory efficient packet matching FPGA architecture for future high-speed networks. Microprocessors and Microsystems, vol. 73, no. 3, 2020, pp. 1-12. ISSN 0141-9331. Detail

2019

VRÁNA Roman, KOŘENEK Jan and NOVÁK David. Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic. In: Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019. Cluj-Napoca: Institute of Electrical and Electronics Engineers, 2019, pp. 1-6. ISBN 978-1-7281-0073-9. Detail
FUKAČ Tomáš and KOŘENEK Jan. Hash-based Pattern Matching for High Speed Networks. In: Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019. Cluj-Napoca: Institute of Electrical and Electronics Engineers, 2019, pp. 1-5. ISBN 978-1-7281-0073-9. Detail
WRONA Jan and ŽÁDNÍK Martin. Low Overhead Distributed IP Flow Records Collection and Analysis. In: 2019 IFIP/IEEE International Symposium on Integrated Network Management. Washington DC, 2019, pp. 557-562. ISBN 978-3-903176-15-7. Detail

2018

KEKELY Michal, KEKELY Lukáš and KOŘENEK Jan. Memory Aware Packet Matching Architecture for High-Speed Networks. In: Proceedings of the 21st Euromicro Conference on Digital Systems Design. Praha: IEEE Computer Society, 2018, pp. 1-8. ISBN 978-1-5386-7376-8. Detail

2017

KEKELY Michal and KOŘENEK Jan. Mapping of P4 Match Action Tables to FPGA. In: Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS. Ghent: Institute of Electrical and Electronics Engineers, 2017, pp. 1-2. ISBN 978-90-90-30428-1. Detail
KEKELY Michal and KOŘENEK Jan. Packet Classification with Limited Memory Resources. In: In proceedings 2017 Euromicro Conference on Digital System Design. Vieden: Institute of Electrical and Electronics Engineers, 2017, pp. 179-183. ISBN 978-1-5386-2145-5. Detail

2016

DOBAI Roland, KOŘENEK Jan and SEKANINA Lukáš. Adaptive Development of Hash Functions in FPGA-Based Network Routers. In: 2016 IEEE Symposium Series on Computational Intelligence. Athens: IEEE Computational Intelligence Society, 2016, pp. 1-8. ISBN 978-1-5090-4240-1. Detail
KOŠAŘ Vlastimil and KOŘENEK Jan. Dynamically Reconfigurable Architecture with Atomic Configuration Updates for Flexible Regular Expressions Matching in FPGA. In: Proceedings of The 19th Euromicro Conference on Digital Systems Design. Limassol: IEEE Computer Society, 2016, pp. 591-598. ISBN 978-1-5090-2816-0. Detail
KOŘENEK Jan and VIKTORIN Jan. Packet Processing on FPGA SoC with DPDK. In: 26th International Conference on Field-Programmable Logic and Applications. Lausanne: École Polytechnique Fédérale de Lausanne, 2016, pp. 578-579. ISBN 978-2-8399-1844-2. Detail

Products

2019

Lawful Interception L7 Probe for 10 Gbps networks, specimen, 2019
Authors: Dražil Jan, Fukač Tomáš, Košař Vlastimil, Polčák Libor, Vrána Roman, Kekely Lukáš, Korček Pavol, Kořenek Jan Detail

2018

Hardware platform for network embedded devices with 10 Gbps network links, specimen, 2018
Authors: Sikora Jiří, Košař Vlastimil, Fukač Tomáš, Orsák Michal, Dražil Jan, Kořenek Jan Detail
Library of acceleration components for analysis of application-layer protocols on FPGA, software, 2018
Authors: Košař Vlastimil, Selecký Roman, Kořenek Jan, Fukač Tomáš Detail

2017

Lawful Interception L7 Probe, specimen, 2017
Authors: Dražil Jan, Fukač Tomáš, Kekely Lukáš, Košař Vlastimil, Polčák Libor, Korček Pavol, Kořenek Jan Detail
Packet Stack, software, 2017
Authors: Polčák Libor, Franková Barbora, Kekely Lukáš, Vrána Roman, Dražil Jan Detail