Project Details

Sondy pro analýzu a filtraci provozu na úrovni aplikačních protokolů

Project Period: 1. 9. 2015 – 31. 5. 2019

Project Type: grant

Code: VI20152019001

Agency: Ministerstvo vnitra ČR

Program: Bezpečnostní výzkum České republiky 2015-2020

English title
Smart Application Aware Embedded Probes
Type
grant
Keywords

lawful interception, application protocol, probe, FPGA

Abstract

The aim of the project is to create small and flexible network probes capable of
lawful interception up to the application layer, to be used by the law
enforcement agencies. The concept of software defined monitoring and the FPGA SoC
computation platform will be used to achieve the required performance. The probe
will, besides the detailed traffic analysis and filtering, provide statistical
information and the information regarding the quality of the measured data. It
will also identify the encrypted traffic and adjust the data acquisition to the
available hardware resources.

Team members
Kořenek Jan, doc. Ing., Ph.D. (DCSY) – research leader
Dobai Roland, Ing., Ph.D. (CM-SFE)
Korček Pavol, Ing., Ph.D. (DCSY)
Košař Vlastimil, Ing., Ph.D. (DCSY)
Puš Viktor, Ing., Ph.D.
Viktorin Jan, Ing.
Žádník Martin, Ing., Ph.D. (DCSY)
Publications

2020

  • KEKELY, M.; KEKELY, L.; KOŘENEK, J. General memory efficient packet matching FPGA architecture for future high-speed networks. Microprocessors and Microsystems, 2020, vol. 73, no. 3, p. 1-12. ISSN: 0141-9331. Detail

2019

  • FUKAČ, T.; KOŘENEK, J. Hash-based Pattern Matching for High Speed Networks. In Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019. Cluj-Napoca: Institute of Electrical and Electronics Engineers, 2019. p. 1-5. ISBN: 978-1-7281-0073-9. Detail
  • VRÁNA, R.; KOŘENEK, J.; NOVÁK, D. Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic. In Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019. Cluj-Napoca: Institute of Electrical and Electronics Engineers, 2019. p. 1-6. ISBN: 978-1-7281-0073-9. Detail
  • WRONA, J.; ŽÁDNÍK, M. Low Overhead Distributed IP Flow Records Collection and Analysis. In 2019 IFIP/IEEE International Symposium on Integrated Network Management. Washington DC: 2019. p. 557-562. ISBN: 978-3-903176-15-7. Detail

2018

  • KEKELY, M.; KEKELY, L.; KOŘENEK, J. Memory Aware Packet Matching Architecture for High-Speed Networks. In Proceedings of the 21st Euromicro Conference on Digital Systems Design. Praha: IEEE Computer Society, 2018. p. 1-8. ISBN: 978-1-5386-7376-8. Detail

2017

  • KEKELY, M.; KOŘENEK, J. Mapping of P4 Match Action Tables to FPGA. In Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS. Ghent: Institute of Electrical and Electronics Engineers, 2017. p. 1-2. ISBN: 978-90-90-30428-1. Detail
  • KEKELY, M.; KOŘENEK, J. Packet Classification with Limited Memory Resources. In In proceedings 2017 Euromicro Conference on Digital System Design. Vieden: Institute of Electrical and Electronics Engineers, 2017. p. 179-183. ISBN: 978-1-5386-2145-5. Detail

2016

  • DOBAI, R.; KOŘENEK, J.; SEKANINA, L. Adaptive Development of Hash Functions in FPGA-Based Network Routers. In 2016 IEEE Symposium Series on Computational Intelligence. Athens: IEEE Computational Intelligence Society, 2016. p. 1-8. ISBN: 978-1-5090-4240-1. Detail
  • KOŘENEK, J.; VIKTORIN, J. Packet Processing on FPGA SoC with DPDK. In 26th International Conference on Field-Programmable Logic and Applications. Lausanne: École Polytechnique Fédérale de Lausanne, 2016. p. 578-579. ISBN: 978-2-8399-1844-2. Detail
  • KOŠAŘ, V.; KOŘENEK, J. Dynamically Reconfigurable Architecture with Atomic Configuration Updates for Flexible Regular Expressions Matching in FPGA. In Proceedings of The 19th Euromicro Conference on Digital Systems Design. Limassol: IEEE Computer Society, 2016. p. 591-598. ISBN: 978-1-5090-2816-0. Detail
Products

2019

2018

2017

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