Project Details

Evoluční postupy pro zvýšení testovatelnosti číslicových obvodů

Project Period: 1. 1. 2002 - 31. 12. 2002

Project Type: grant

Code: FR1754/2002/G1

Agency: Fond rozvoje vysokých škol MŠMT

Program:

English title
Application of Evolution Approaches for Digital Circuit Testability Enhancement
Type
grant
Keywords

controllability, observability, testability, testability analysis, evolution approach, design for test, scan, test point insertion technique

Abstract

With increasing digital circuits complexity and reducing the time-to-value and time-to-market values, efforts are growing how to at very short time and certainly test if a produced die does a function it was designed for. Thus, automated techniques evaluating digital circuit testability measures exist. These techniques are able to detect difficult-to-test nodes and to suggest the proper digital circuit structure modification leading to digital circuit testability enhancement. In the frame of our project, these so called testability analysis and enhancement techniques are based on evolutionary approaches and they can be characterized especially by their fast convergence to the searched solution - in our case to optimal (with respect to designer's claims) digital circuit testability.

Team members
Strnadel Josef, Ing., Ph.D. (UPSY FIT VUT) , research leader
Kotásek Zdeněk, doc. Ing., CSc. (UPSY FIT VUT) , team leader
Publications

2003

  • STRNADEL Josef. Analýza a zlepšení testovatelnosti RTL číslicového obvodu. In: Sborník příspěvků ze semináře Počítačové Architektury & Diagnostika. Brno: Faculty of Information Technology BUT, 2003, pp. 24-29. ISBN 80-214-2471-0. Detail

2002

  • STRNADEL Josef. Evaluating Cost/Quality Trade-off Solutions Proposed During a DFT Process. In: Proceeding of 8th Conference Student EEICT 2002. Brno: Brno University of Technology, 2002, pp. 506-510. ISBN 80-214-2116-9. Detail
  • STRNADEL Josef and KOTÁSEK Zdeněk. Normalized Testability Measures at RT Level: Utilization and Reasons for Creation. In: Proceedings of 36th International Conference MOSIS`02 Modeling and Simulation of Systems. Vol. I.. Ostrava, 2002, pp. 297-304. ISBN 80-85988-71-2. Detail
  • STRNADEL Josef. Normalized Testability Measures Based on RTL Digital Circuit Graph Model Analysis. In: Proceedings of The fifth International Scientific Conference Electronic Computers and Informatics 2002. Edition 55. Košice: The University of Technology Košice, 2002, pp. 200-205. ISBN 80-7099-879-2. Detail
  • STRNADEL Josef and KOTÁSEK Zdeněk. Optimising Solution of the Scan Problem at RT Level Based on a Genetic Algorithm. In: Proceedings of 5th IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop. Brno: Brno University of Technology, 2002, pp. 44-51. ISBN 80-214-2094-4. Detail
  • STRNADEL Josef and KOTÁSEK Zdeněk. Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. In: Proceedings of Euromicro Symposium on Digital System Design Architectures, Methods and Tools DSD'2002. Los Alamitos: IEEE Computer Society Press, 2002, pp. 166-173. ISBN 0-7695-1790-0. Detail
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