Project Details

SECREDAS - Product Security for Cross Domain Reliable Dependable Automated Systems

Project Period: 1. 5. 2018 - 30. 4. 2021

Project Type: grant

Code: 8A18014, Proposal ID 783119-2

Agency: ECSEL Joint Undertaking

Program: Společná technologická iniciativa ECSEL

Czech title
Produktová bezpečnost pro spolehlivé automatizované systémy napříč obory
Type
grant
Keywords

security, vehicle, automotive, safety

Abstract

The high-level goal of SECREDAS is to develop and validate multi-domain architecting methodologies, reference architectures, components and suitable integration and verification approaches for automated systems in different domains, combining high security and privacy protection while preserving functional-safety and operational performance.

Team members
Smrž Pavel, doc. RNDr., Ph.D. (UPGM FIT VUT) , research leader
Fiedler Petr, doc. Ing., Ph.D. (UAMT FEKT VUT) , team leader
Publications

2021

  • LOJDA Jakub, PÁNEK Richard and KOTÁSEK Zdeněk. Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs. In: Proceedings - 2021 24th Euromicro Conference on Digital System Design, DSD 2021. Palermo: Institute of Electrical and Electronics Engineers, 2021, pp. 549-552. ISBN 978-1-6654-2703-6. Detail
  • PÁNEK Richard, LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Reliability Analysis of the FPGA Control System with Reconfiguration Hardening. In: Proceedings - 2021 24th Euromicro Conference on Digital System Design, DSD 2021. Palermo: Institute of Electrical and Electronics Engineers, 2021, pp. 553-556. ISBN 978-1-6654-2703-6. Detail
  • LOJDA Jakub, PÁNEK Richard, PODIVÍNSKÝ Jakub, ČEKAN Ondřej, KRČMA Martin and KOTÁSEK Zdeněk. Testing Embedded Software Through Fault Injection: Case Study on Smart Lock. In: 2021 IEEE 22nd Latin American Test Symposium, LATS 2021. Punta del Este: Institute of Electrical and Electronics Engineers, 2021, pp. 80-85. ISBN 978-1-6654-2057-0. Detail

2020

  • LOJDA Jakub, PÁNEK Richard, PODIVÍNSKÝ Jakub, ČEKAN Ondřej, KRČMA Martin and KOTÁSEK Zdeněk. Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock. In: 2020 IEEE East-West Design and Test Symposium, EWDTS 2020 - Proceedings. Varna: Institute of Electrical and Electronics Engineers, 2020, pp. 24-28. ISBN 978-1-7281-9899-6. Detail
  • LOJDA Jakub, PODIVÍNSKÝ Jakub, ČEKAN Ondřej, PÁNEK Richard, KRČMA Martin and KOTÁSEK Zdeněk. Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. In: Proceedings - 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020. Novi Sad: Institute of Electrical and Electronics Engineers, 2020, pp. 1-4. ISBN 978-1-7281-9938-2. Detail
  • PODIVÍNSKÝ Jakub, LOJDA Jakub, PÁNEK Richard, ČEKAN Ondřej, KRČMA Martin and KOTÁSEK Zdeněk. Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks. In: 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS). San José: IEEE Circuits and Systems Society, 2020, pp. 1-4. ISBN 978-1-7281-3427-7. Detail
  • LOJDA Jakub, PÁNEK Richard, PODIVÍNSKÝ Jakub, ČEKAN Ondřej, KRČMA Martin and KOTÁSEK Zdeněk. Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. In: Proceedings - Euromicro Conference on Digital System Design, DSD 2020. Kranj: Institute of Electrical and Electronics Engineers, 2020, pp. 680-683. ISBN 978-1-7281-9535-3. Detail
  • PÁNEK Richard, LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study. In: 2020 International Symposium on VLSI Design, Automation, and Test (VLSI-DAT) : proceedings of technical papers. Hsinchu: IEEE Computer Society, 2020, pp. 121-124. ISBN 978-1-7281-6083-2. Detail

2019

  • KRČMA Martin, KOTÁSEK Zdeněk and LOJDA Jakub. Detecting hard synapses faults in artificial neural networks. In: 20th IEEE Latin American Test Symposium (LATS 2019). Santiago de Chile: IEEE Computer Society, 2019, pp. 1-6. ISBN 978-1-7281-1756-0. Detail
  • PODIVÍNSKÝ Jakub, LOJDA Jakub and KOTÁSEK Zdeněk. Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. In: 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019, pp. 97-100. ISBN 978-1-7281-1756-0. Detail
  • LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. In: 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019, pp. 93-96. ISBN 978-1-7281-1756-0. Detail
  • ČEKAN Ondřej, PODIVÍNSKÝ Jakub, LOJDA Jakub, PÁNEK Richard, KRČMA Martin and KOTÁSEK Zdeněk. Smart Electronic Locks and Their Reliability. In: Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy: Czech Technical University, 2019, pp. 4-5. ISBN 978-80-01-06607-2. Detail
  • ČEKAN Ondřej, PODIVÍNSKÝ Jakub, LOJDA Jakub, PÁNEK Richard, KRČMA Martin and KOTÁSEK Zdeněk. Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. In: Proceedings of the 2019 22nd Euromicro Conference on Digital System Design. Kalithea: Institute of Electrical and Electronics Engineers, 2019, pp. 506-513. ISBN 978-1-7281-2861-0. Detail

2018

  • PODIVÍNSKÝ Jakub, LOJDA Jakub and KOTÁSEK Zdeněk. An Experimental Evaluation of Fault-Tolerant FPGA-based Robot Controller. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, pp. 63-69. ISBN 978-1-5386-5710-2. Detail
  • LOJDA Jakub and KOTÁSEK Zdeněk. Automatizace návrhu spolehlivých systémů a její dílčí komponenty. In: Počítačové architektury & diagnostika 2018. Stachy: University of West Bohemia in Pilsen, 2018, pp. 5-8. ISBN 978-80-261-0814-6. Detail
  • LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, pp. 80-86. ISBN 978-1-5386-5710-2. Detail
  • ČEKAN Ondřej, PÁNEK Richard and KOTÁSEK Zdeněk. Input and Output Generation for the Verification of ALU: a Use Case. In: Proceedings of 2018 IEEE East-West Design and Test Symposium, EWDTS 2018. Kazan: IEEE Computer Society, 2018, pp. 331-336. ISBN 978-1-5386-5710-2. Detail
  • LOJDA Jakub, PODIVÍNSKÝ Jakub, KOTÁSEK Zdeněk and KRČMA Martin. Majority Type and Redundancy Level Influences on Redundant Data Types Approach for HLS. In: 2018 16th Biennial Baltic Electronics Conference (BEC). Tallinn: IEEE Computer Society, 2018, pp. 1-4. ISBN 978-1-5386-7312-6. Detail
  • PÁNEK Richard. Metodika návrhu řadiče rekonfigurace pro Systémy odolné proti poruchám. In: Počítačové architektury & diagnostika 2018. Stachy: University of West Bohemia in Pilsen, 2018, pp. 21-24. ISBN 978-80-261-0814-6. Detail
  • PÁNEK Richard, LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. In: Proceedings of IEEE East-West Design & Test Symposium. Kazaň: IEEE Computer Society, 2018, pp. 129-134. ISBN 978-1-5386-5710-2. Detail
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