Project Details

Navrhování a využívání knihoven aproximativních obvodů

Project Period: 1. 1. 2019 - 31. 12. 2021

Project Type: grant

Code: GA19-10137S

Agency: Czech Science Foundation

Program: Standardní projekty

English title
Designing and exploiting libraries of approximate circuits
Type
grant
Keywords

approximate circuit, computer aided design, genetic programming, evolvable hardware, digital circuit library

Abstract

Approximate circuits are building blocks of complex systems on a chip that can exchange the quality of processing for power consumption reduction. The design of an approximate circuit showing good tradeoffs between the error and other parameters is still a challenging task. We propose to reduce the design time and increase the complexity of circuits that can routinely be approximated by (i) developing a comprehensive library of elementary approximate circuits and (ii) introducing suitable compositional schemes exploiting the elementary circuits available in the library. Assembling a complex approximate circuit from approximate sub-circuits is a challenging problem as it is, in general, unclear how to perform the (de)composition and how the errors of these sub-circuits manifest at the global level. The project seeks the following contributions: (1) efficient deterministic and evolutionary compositional algorithms for approximate circuit design, (2) a library containing over 1 million approximate circuits, and (3) new knowledge about approximate circuits by analyzing the library.

Team members
Sekanina Lukáš, prof. Ing., Ph.D. (UPSY FIT VUT) , research leader
Bidlo Michal, doc. Ing., Ph.D. (UPSY FIT VUT)
Drahošová Michaela, Ing., Ph.D. (UPSY FIT VUT)
Husa Jakub, Ing., Ph.D. (UPSY FIT VUT)
Chlebík Jakub, Ing. (UPSY FIT VUT)
Klhůfek Jan, Ing. (FIT VUT)
Kocnová Jitka, Ing., Ph.D. (UPSY FIT VUT)
Mrázek Vojtěch, Ing., Ph.D. (UPSY FIT VUT)
Piňos Michal, Ing. (FIT VUT)
Strnadel Josef, Ing., Ph.D. (UPSY FIT VUT)
Vašíček Zdeněk, doc. Ing., Ph.D. (UPSY FIT VUT)
Publications

2022

  • STRNADEL Josef. Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking. In: Proceedings of 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Prague: Institute of Electrical and Electronics Engineers, 2022, pp. 88-93. ISBN 978-1-6654-9431-1. Detail
  • SEKANINA Lukáš, VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Inexact Arithmetic Operators. Approximate Computing Techniques. Cham: Springer International Publishing, 2022, pp. 81-107. ISBN 978-3-030-94704-0. Detail

2021

  • MARCHISIO Alberto, MRÁZEK Vojtěch, HANIF Muhammad A. and SHAFIQUE Muhammad. DESCNet: Developing Efficient Scratchpad Memories for Capsule Network Hardware. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 9, 2021, pp. 1768-1781. ISSN 1937-4151. Detail
  • CHLEBÍK Jakub and JAROŠ Jiří. Distributed Evolutionary Design of High Intensity Focused Ultrasound Treatment Plans. In: IEEE International Conference on Systems, Man and Cybernetics . Melbourne: IEEE Circuits and Systems Society, 2021, pp. 2203-2208. ISBN 978-1-6654-4207-7. Detail
  • BIDLO Michal. Evolution of Approximate Functions for Image Thresholding. In: IEEE Symposium Series on Computational Intelligence (IEEE SSCI). Los Alamos: IEEE Computer Society, 2021, pp. 1-6. ISBN 978-1-7281-9048-8. Detail
  • MARCHISIO Alberto, MRÁZEK Vojtěch, HANIF Muhammad A. and SHAFIQUE Muhammad. FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 4, 2021, pp. 716-729. ISSN 1063-8210. Detail
  • KOCNOVÁ Jitka and VAŠÍČEK Zdeněk. Resynthesis of logic circuits using machine learning and reconvergent paths. In: 2021 24th Euromicro Conference on Digital System Design (DSD). Palermo: Institute of Electrical and Electronics Engineers, 2021, pp. 69-76. ISBN 978-1-6654-2704-3. Detail
  • HODAŇ David, MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. Genetic Programming and Evolvable Machines, vol. 22, no. 4, 2021, pp. 539-572. ISSN 1389-2576. Detail
  • VAŠÍČEK Zdeněk. Synthesis of approximate circuits for LUT-based FPGAs. In: 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Vienna: IEEE Computer Society, 2021, pp. 17-22. ISBN 978-1-6654-3595-6. Detail
  • STRNADEL Josef. Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults. In: Proceedings of 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Vienna: Institute of Electrical and Electronics Engineers, 2021, pp. 111-114. ISBN 978-1-6654-3595-6. Detail

2020

  • PRABAKARAN Bharath S., MRÁZEK Vojtěch, VAŠÍČEK Zdeněk, SEKANINA Lukáš and SHAFIQUE Muhammad. ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems. In: 2020 57th ACM/IEEE Design Automation Conference (DAC). San Francisco: Institute of Electrical and Electronics Engineers, 2020, pp. 1-6. ISBN 978-1-4503-6725-7. Detail
  • BOSIO Alberto, DI Carlo Stefano, GIRARD Patrick, SANCHEZ Ernesto, SAVINO Aessandro, SEKANINA Lukáš, TRAIOLA Marcello, VAŠÍČEK Zdeněk and VIRAZEL Arnaud. Design, Verification, Test and In-Field Implications of Approximate Computing Systems. In: 25th IEEE European Test Symposium. Los Alamitos: Institute of Electrical and Electronics Engineers, 2020, pp. 1-10. ISBN 978-1-7281-4312-5. Detail
  • KOCNOVÁ Jitka and VAŠÍČEK Zdeněk. EA-based Resynthesis: An Efficient Tool for Optimization of Digital Circuits. Genetic Programming and Evolvable Machines, vol. 21, no. 3, 2020, pp. 287-319. ISSN 1389-2576. Detail
  • BIDLO Michal. Evolution of Cellular Automata with Conditionally Matching Rules for Image Filtering. In: 2020 IEEE Congress on Evolutionary Computation (CEC). Los Alamitos: IEEE Computational Intelligence Society, 2020, pp. 1-8. ISBN 978-1-7281-6929-3. Detail
  • HUSA Jakub and SEKANINA Lukáš. Evolving Cryptographic Boolean Functions with Minimal Multiplicative Complexity. In: 2020 IEEE Congress on Evolutionary Computation (CEC). Los Alamitos: IEEE Computational Intelligence Society, 2020, pp. 1-8. ISBN 978-1-7281-6929-3. Detail
  • MRÁZEK Vojtěch, SEKANINA Lukáš and VAŠÍČEK Zdeněk. Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 10, no. 4, 2020, pp. 406-418. ISSN 2156-3357. Detail
  • NEVORAL Jan, ŠIMEK Václav and RŮŽIČKA Richard. Power Consumption Analysis of New Generation of Polymorphic Gates. In: 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020. Novi Sad: Institute of Electrical and Electronics Engineers, 2020, pp. 1-6. ISBN 978-1-7281-9938-2. Detail
  • MARCHISIO Alberto, MRÁZEK Vojtěch, HANIF Muhammad A. and SHAFIQUE Muhammad. ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations. In: Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. Grenoble: Institute of Electrical and Electronics Engineers, 2020, pp. 1205-1210. ISBN 978-3-9819263-4-7. Detail
  • STRNADEL Josef. Statistical Model Checking of Approximate Circuits: Challenges and Opportunities. In: Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). Grenoble: IEEE Computer Society, 2020, pp. 1574-1577. ISBN 978-3-9819263-4-7. Detail
  • VAVERKA Filip, MRÁZEK Vojtěch, VAŠÍČEK Zdeněk and SEKANINA Lukáš. TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). Grenoble: Institute of Electrical and Electronics Engineers, 2020, pp. 294-297. ISBN 978-3-9819263-4-7. Detail
  • MRÁZEK Vojtěch, SEKANINA Lukáš and VAŠÍČEK Zdeněk. Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. In: 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems. Genoa: Institute of Electrical and Electronics Engineers, 2020, pp. 243-247. ISBN 978-1-7281-4922-6. Detail

2019

  • MRÁZEK Vojtěch, VAŠÍČEK Zdeněk, SEKANINA Lukáš, HANIF Muhammad A. and SHAFIQUE Muhammad. ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Denver: Institute of Electrical and Electronics Engineers, 2019, pp. 1-8. ISBN 978-1-7281-2350-9. Detail
  • MRÁZEK Vojtěch, HANIF Muhammad A., VAŠÍČEK Zdeněk, SEKANINA Lukáš and SHAFIQUE Muhammad. autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. In: The 56th Annual Design Automation Conference 2019 (DAC '19). Las Vegas: Association for Computing Machinery, 2019, pp. 1-6. ISBN 978-1-4503-6725-7. Detail
  • VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Automated Circuit Approximation Method Driven by Data Distribution. In: Design, Automation and Test in Europe Conference. Florence: European Design and Automation Association, 2019, pp. 96-101. ISBN 978-3-9819263-2-3. Detail
  • HUSA Jakub. Comparison of Genetic Programming Methods on Design of Cryptographic Boolean Functions. In: Genetic Programming 22st European Conference, EuroGP 2019, Proceedings. Cham: Springer International Publishing, 2019, pp. 228-244. ISBN 978-3-030-14811-9. Detail
  • HUSA Jakub. Designing Correlation Immune Boolean Functions With Minimal Hamming Weight Using Various Genetic Programming Methods. In: GECCO '19 Proceedings of the Genetic and Evolutionary Computation Conference Companion. Praha: Association for Computing Machinery, 2019, pp. 342-343. ISBN 978-1-4503-6748-6. Detail
  • KOCNOVÁ Jitka and VAŠÍČEK Zdeněk. EA-based refactoring of mapped logic circuits. In: 2019 IEEE International Symposium on Circuits and Systems (ISCAS). Red Hook, NY: IEEE Computer Society Press, 2019, pp. 1-5. ISBN 978-1-7281-0397-6. Detail
  • VAŠÍČEK Zdeněk. Formal Methods for Exact Analysis of Approximate Circuits. IEEE Access, vol. 7, no. 1, 2019, pp. 177309-177331. ISSN 2169-3536. Detail
  • REK Petr and SEKANINA Lukáš. TypeCNN: CNN Development Framework With Flexible Data Types. In: Design, Automation and Test in Europe Conference. Florence: European Design and Automation Association, 2019, pp. 292-295. ISBN 978-3-9819263-2-3. Detail
Products

2019

  • EvoApproxLib - a comprehensive collection of low-level approximate implementations of arithmetic operations, software, 2019
    Authors: Mrázek Vojtěch, Vašíček Zdeněk, Sekanina Lukáš Detail
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