Project Details

Evoluční návrh testovacích obvodů

Project Period: 1. 1. 2005 - 31. 12. 2005

Project Type: grant

Code: FR3041/2005/G1

Agency: Fond rozvoje vysokých škol MŠMT

Program:

English title

Evolutionary Design of Benchmark Circuits

Type

grant

Keywords

benchmark circuits, evolutionary design, evolutionary programming

Abstract

The project deals with develop a method for generation of synthetic benchmark circuits on register transfer level. In the project, the new approach, which utilizes evolutionary techniques for design a benchmark circuits with predefined structure and diagnostic properties (in terms of controllability and observability) is presented. Graph representation of the circuit is used for generation of benchmark circuits and circuit structure analysis. Testability analysis is performed by testability analysis tool developed on FIT BUT. The output of developed tool is in form of circuit described in synthesisable VHDL code.

Team members

Pečenka Tomáš, Ing. (UPSY FIT VUT) , research leader
Kotásek Zdeněk, doc. Ing., CSc. (UPSY FIT VUT) , team leader

Publications

2008

PEČENKA Tomáš. Prostředky a metody pro automatické generování testovacích obvodů. Brno: Faculty of Information Technology BUT, 2008. ISBN 978-80-214-3603-9. Detail

2005

PEČENKA Tomáš, KOTÁSEK Zdeněk, SEKANINA Lukáš and STRNADEL Josef. Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. In: Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2005, pp. 51-58. ISBN 0-7695-2399-4. Detail
PEČENKA Tomáš. Prostředky a metody pro automatické vytváření testovacích obvodů. In: Sborník příspěvků ze semináře Počítačové Architektury a Diagnostika. Praha: Faculty of Electrical Engineering, Czech Technical University, 2005, pp. 135-140. ISBN 80-01-03298-1. Detail