Project Details

SoC circuits reliability and availability improvement

Project Period: 1. 1. 2009 - 31. 12. 2011

Project Type: grant

Code: GA102/09/1668

Agency: Czech Science Foundation

Program: Standardní projekty

Czech title
Zvyšování spolehlivost a provozuschopnosti v obvodech SoC
Type
grant
Keywords

fault tolerant systems, dependability

Abstract

We propose a basic research project that is aimed at utilizing and deepening the current results of three research groups in the field of on-line and off-line testing and diagnostics with the intension to utilize them in the design of fault tolerant systems. The fault tolerant methodologies will be developed on three levels: level of error tolerance, level of single-event upset detection with additional reconfiguration and a level of system architecture graceful degradation in case of unrecoverable faults appearance. The goal of this project is to design a new, advanced design methodology for fault-tolerant circuits that will be based on the new technological possibilities.

Team members
Kotásek Zdeněk, doc. Ing., CSc. (UPSY FIT VUT) , research leader
Bartoš Pavel, Ing. (UPSY FIT VUT) , team leader
Kaštil Jan, Ing. (UPSY FIT VUT) , team leader
Mičulka Lukáš, Ing. (UPSY FIT VUT) , team leader
Slimařík František, Ing. (UPSY FIT VUT) , team leader
Straka Martin, Ing., Ph.D. (UPSY FIT VUT) , team leader
Strnadel Josef, Ing., Ph.D. (UPSY FIT VUT) , team leader
Publications

2011

  • STRAKA Martin, KAŠTIL Jan, NOVOTNÝ Jaroslav and KOTÁSEK Zdeněk. Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011, pp. 397-398. ISBN 978-1-4244-9753-9. Detail
  • STRNADEL Josef. Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads. In: Proceedings of the Work in Progress Session held in connection with SEAA 2011, the 37th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2011, the 14th EUROMICRO Conference on Digital System Design. Oulu: Johannes Kepler University Linz, 2011, pp. 21-22. ISBN 978-3-902457-30-1. Detail
  • BARTOŠ Pavel, KOTÁSEK Zdeněk and DOHNAL Jan. Decreasing Test Time by Scan Chain Reorganization. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011, pp. 371-374. ISBN 978-1-4244-9753-9. Detail
  • BARTOŠ Pavel, KOTÁSEK Zdeněk and DOHNAL Jan. Decreasing Test Time by Scan Chain Reorganization. 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Brno University of Technology, 2011. ISBN 978-80-214-4305-1. Detail
  • RŮŽIČKA Richard and ŠIMEK Václav. Chip Temperature Selfregulation for Digital Circuits Using Polymorphic Electronics Principles. In: Proceedings of 14th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2011, pp. 205-212. ISBN 978-0-7695-4494-6. Detail
  • MIČULKA Lukáš. Metoda návrh systémů odolných proti poruchám do omezeného implementačního prostoru na bázi FPGA. In: Počítačové architektury & diagnostika 2011. Bratislava: Faculty of Informatics and Information Technology Slovak University of Technology in Bratislava, 2011, pp. 61-66. ISBN 978-80-227-3552-0. Detail
  • BARTOŠ Pavel. Metody optimalizace propojení scan řetězce. In: Počítačové architektury a diagnostika 2011. Bratislava: Vydavateľstvo STU, 2011, pp. 97-102. ISBN 978-80-227-3552-0. Detail
  • RUMPLÍK Michal and STRNADEL Josef. On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits. In: Proceedings of the 14th Euromicro Conference on Digital System Design - Architectures, Methods and Tools 2011. Oulu: IEEE Computer Society, 2011, pp. 367-374. ISBN 978-0-7695-4494-6. Detail
  • STRNADEL Josef. Proposal of Flexible Monitoring-Driven HW/SW Interrupt Management for Embedded COTS-Based Event-Triggered Real-Time Systems. In: Proceedings of the Work-in-Progress Session of the 32nd IEEE Real-Time Systems Symposium. Vienna: Technical University Wien, 2011, pp. 29-32. Detail
  • STRAKA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems. In: 14th EUROMICRO Conference on Digital System Design. Oulu: IEEE Computer Society, 2011, pp. 223-230. ISBN 978-0-7695-4494-6. Detail
  • BARTOŠ Pavel. Test Time Reduction by Scan Chain Reordering. In: Proceedings of the 17th Conference STUDENT EEICT 2011. Volume 3. Brno: Faculty of Electrical Engineering and Communication BUT, 2011, pp. 564-568. ISBN 978-80-214-4273-3. Detail

2010

  • STRAKA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration. In: 13th EUROMICRO Conference on Digital System Design, DSD'2010. Lille: IEEE Computer Society, 2010, pp. 365-372. ISBN 978-0-7695-4171-6. Detail
  • STRAKA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA. In: NORCHIP 2010. Tampere: IEEE Computer Society, 2010, pp. 1-4. ISBN 978-1-4244-8971-8. Detail
  • RŮŽIČKA Richard. Gracefully Degrading Circuit Controllers Based on Polytronics. In: Proc. of 13th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2010, pp. 809-812. ISBN 978-0-7695-4171-6. Detail
  • STRAKA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. Methodology for Design of Highly Dependable Systems in FPGA. In: International Scientific Conference on Computer Science and Engineering. Košice: The University of Technology Košice, 2010, pp. 186-193. ISBN 978-80-8086-164-3. Detail
  • STRAKA Martin. Metodika pro návrh číslicových systémů se zvýšenou spolehlivostí v obvodech FPGA. In: Počítačové architektury a diagnostika 2010. Brno: Faculty of Information Technology BUT, 2010, pp. 159-164. ISBN 978-80-214-4140-8. Detail
  • STRAKA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs. In: Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Wien: IEEE Computer Society, 2010, pp. 173-176. ISBN 978-1-4244-6610-8. Detail
  • STRNADEL Josef. Návrh časově kritických systémů I: specifikace a verifikace. Automa, vol. 2010, no. 10, pp. 42-44. ISSN 1210-9592. Detail
  • FIŠER Petr, SCHMIDT Jan, VAŠÍČEK Zdeněk and SEKANINA Lukáš. On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming. In: Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010, pp. 346-351. ISBN 978-1-4244-6610-8. Detail
  • ŠKARVADA Jaroslav, KOTÁSEK Zdeněk and STRNADEL Josef. Optimalizace aplikace testu číslicových systémů pro nízký příkon. Brno: Faculty of Information Technology BUT, 2010. ISBN 978-80-214-4209-2. Detail
  • BARTOŠ Pavel. Optimalizace propojení řetězce scan po ukončení fyzického návrhu. In: Počítačové architektury a diagnostika 2010. Brno: Faculty of Information Technology BUT, 2010, pp. 21-26. ISBN 978-80-214-4140-8. Detail
  • KOTÁSEK Zdeněk, ŠKARVADA Jaroslav and STRNADEL Josef. Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences. In: Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010, pp. 364-369. ISBN 978-1-4244-6610-8. Detail
  • STRNADEL Josef. Task-Level Modeling and Design of Components for Construction of Dependable Time-Critical Systems Implemented by Means of RT Kernel. In: Sborník přednášek z 33. mezinárodní konference TD 2010 - DIAGON 2010. Zlín: Tomas Bata University in Zlín, 2010, pp. 99-104. ISBN 978-80-7318-940-2. Detail
  • KOTÁSEK Zdeněk, ŠKARVADA Jaroslav and STRNADEL Josef. The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. In: Proceedings of 13th Euromicro Conference on Digital System Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2010, pp. 644-651. ISBN 978-0-7695-4171-6. Detail
  • ŠKARVADA Jaroslav, KOTÁSEK Zdeněk and STRNADEL Josef. The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. In: Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science, ISSN 0302-9743, Vol. 6274, vol. 2010. Berlin: Springer Verlag, 2010, pp. 181-192. ISBN 978-3-642-15322-8. ISSN 0302-9743. Detail

2009

  • STRAKA Martin and KOTÁSEK Zdeněk. High Availability Fault Tolerant Architectures Implemented into FPGAs. In: 12th EUROMICRO Conference on Digital System Design DSD 2009. Patras: IEEE Computer Society, 2009, pp. 108-116. ISBN 978-0-7695-3782-5. Detail
  • STRAKA Martin. Metodologie návrhu obvodů se zvýšenou spolehlivostí založených na FPGA. In: Počítačové architektury a diagnostika 2009. Zlin: Tomas Bata University in Zlín, 2009, pp. 141-146. ISBN 978-80-7318-847-4. Detail
  • STRNADEL Josef. Overview of Mechanisms for Improving Reliability of Embedded Real-Time Systems. In: Proceedings of 32th International Conference TD - DIAGON 2009. Zlín: Tomas Bata University in Zlín, 2009, pp. 19-24. ISBN 978-80-7318-840-5. Detail
  • KOTÁSEK Zdeněk and STRAKA Martin. The Design of On-line Checkers and Their Use in Verification and Testing. Acta Electrotechnica et Informatica, vol. 2009, no. 3, pp. 8-15. ISSN 1335-8243. Detail
Products

2010

  • Tool for scan chain routability visualisation, analysis and optimization, software, 2010
    Authors: Bartoš Pavel, Kotásek Zdeněk Detail
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