Project Details

Využití metod a nástrojů formální verifikace při vývoji pokročilých číslicových systémů

Project Period: 1. 1. 2013 - 31. 12. 2013

Project Type: grant

Code: FR1086/2013/G1

Agency: Fond rozvoje vysokých škol MŠMT

Program: Fond rozvoje vysokých škol (FRVŠ)

English title

Application of methods and techniques of formal verification in the design of advanced digital circuits

Type

grant

Keywords

formal verification, digital circuits

Abstract

This project is aimed at creating new supplementary study and demonstration materials in three current courses of two-year master degree programme Information Technology. The courses are as follows: Hardware/software Codesign (HSC), Design of External Adapters and Embedded Systems (NAV) and Advanced Digital Systems (PCS).

Primary goal of the project is to expound the students the techniques of formal verification used in the area of digital systems design, especially verification based on assertions. Assertions are used to describe specification of the system.

Implementing formal verification methods and steps into the verification process benefits of new abstract view which is completely different from verification methods based on testing producing pseudo-random input vectors to the system and observing its output.

The set of materials will also comprise from use cases of formal verification prepared to be used with the latest verification tools used in the industry. These tools are available at the faculty in its license subscription.

Team members

Zachariášová Marcela, Ing., Ph.D. (UPSY FIT VUT) , research leader
Kajan Michal, Ing. (UPSY FIT VUT) , team leader
Kotásek Zdeněk, doc. Ing., CSc. (UPSY FIT VUT) , team leader

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