Project Details

Vývoj flexibilních číslicových architektur

Project Period: 1. 1. 1995 - 31. 12. 1997

Project Type: grant

Code: GA102/95/1334

Agency: Czech Science Foundation

Program:

English title
Developement of flexible digital architectures
Type
grant
Team members
Dvořák Václav, Prof. Ing., DrSc. (UIVT FEI VUT) , research leader
Cigánek Petr, Ing. (UIVT FEI VUT) , team leader
Drábek Vladimír, doc. Ing., CSc. (UIVT FEI VUT) , team leader
Eysselt Miloš, Ing., CSc. (UIVT FEI VUT) , team leader
Fučík Otto, Dr. Ing. (UIVT FEI VUT) , team leader
Kotásek Zdeněk, Doc. Ing., CSc. (UIVT-VVS FEI VUT) , team leader
Schwarz Josef, Ing., CSc. (UIVT FEI VUT) , team leader
Sllame Azeddien M., Ing. (UIVT FEI VUT) , team leader
Zendulka Jaroslav, Doc. Ing., CSc. (UIVT FEI VUT) , team leader
Publications

1998

  • DVOŘÁK Václav and SLLAME Azeddien M. An FPGA-Based Systolic Serial Multiplier. In: Proceedings of the 5th Electronic Devices and Systems Conference 1998. Brno: unknown, 1998, pp. 394-397. ISBN 80-214-1198-8. Detail

1997

  • EYSSELT Miloš. A Covering of the Boolean Functions. In: Proceedings of the XIXth International Workshop ASIS 1997. Krnov, September 16-18: unknown, 1997, pp. 103-108. ISBN 80-85988-20-8. Detail
  • DVOŘÁK Václav and SCHWARZ Josef. Crosstalk analysis in multiconductor interconnect system. Journal of Electrical Engineering, vol. 48, no. 1-2, 1997, pp. 12-17. ISSN 0013-578X. Detail
  • SCHWARZ Josef. Educational fuzzy development system. In: Proceedings of Conference MOSIS '97. Hradec nad Moravicí, 1997, pp. 233-238. ISBN 80-85988-16-X. Detail
  • SCHWARZ Josef. Experimental study on parallel genetic algorithm for placement optimalization. In: Mendel '97. Brno: Faculty of Mechanical Engineering BUT, 1997, pp. 148-153. ISBN 80-214-0884-7. Detail
  • KOTÁSEK Zdeněk. RT Level Element Classification. In: Proceedings of the DDECS 97. Soláň: unknown, 1997, pp. 41-46. ISBN 80-85988-19-4. Detail
  • BLATNÝ Jan, HLAVIČKA Jan and KOTÁSEK Zdeněk. RT Level Test Scheduling. Computer and Artificial Intelligence, vol. 14, no. 1, 1997, 1997, pp. 13-29. ISSN 0232-0274. Detail
  • KOTÁSEK Zdeněk and ZBOŘIL František. RT Level Testability Analysis In PROLOG Enviroment. In: Proceedings of the DDECS'97. Ostrava, 1997, pp. 47-52. ISBN 80-85988-19-4. Detail
  • KOTÁSEK Zdeněk and ZBOŘIL František. RT Level Testability Analysis to Reduce Test Application Time. In: Proceedings of the EUROMICRO 97. Budapest: unknown, 1997, pp. 104-111. ISBN 0-8186-8129-2. Detail
  • HLAVIČKA Jan, KOTÁSEK Zdeněk and ZBOŘIL František. Test Overhead Reduction through RT Level Testability Analysis. In: Proceedings of the IEEE ETW 1997. Cagliary: unknown, 1997, pp. 43-47. Detail
  • EYSSELT Miloš. The Design of the Factored TANT and TONT Networks. In: Proceedings of the 31st Spring International Conference MOSIS'97. April 28-30, Hradec nad Moravicí: unknown, 1997, pp. 177-182. ISBN 80-85988-18-6. Detail

1996

  • EYSSELT Miloš. A Rounding Problem of the Integers. In: Proceedings of the AMSE Scientific Conference on Communications, Signals and Systems CSS'96. September 10-12, Brno: Faculty of Electrical Engineering and Computer Science BUT, 1996, pp. 55-58. ISBN 80-214-0768-9. Detail
  • DVOŘÁK Václav. Construction of optimum OBDDs using parallel genetic approach. In: Proceedings of the 2nd International Conference MENDEL' 96. Brno: unknown, 1996, pp. 221-222. ISBN 80-214-0769-7. Detail
  • SCHWARZ Josef. Motorola microcontroller as the platform for fuzzy application. In: Proceedings of CSS '96. Brno: unknown, 1996, pp. 239-242. ISBN 80-214-0768-9. Detail
  • ZENDULKA Jaroslav. Program for demonstration of scheduling and allocation in high-level synthesis. In: Proceedings of EDS'96. Brno: Brno University of Technology, 1996, pp. 382-385. ISBN 80-214-0767-8. Detail
  • EYSSELT Miloš. The Comparison of Three One-Bit-at-a-Time Two's Complement Multiplication Methods. In: Proceedings of the AMSE Scientific Conference on Communications, Signals and Systems CSS'96. September 10-12, Brno: Faculty of Electrical Engineering and Computer Science BUT, 1996, pp. 41-44. ISBN 80-214-0768-9. Detail
  • EYSSELT Miloš. The Contribution to a Standard Fixed-Point Division. In: Proceedings of the AMSE Scientific Conference on Communications, Signals and Systems CSS'96. September 10-12, Brno: Faculty of Electrical Engineering and Computer Science BUT, 1996, pp. 37-40. ISBN 80-214-0768-9. Detail
  • SCHWARZ Josef. The FIDE system flexibility in the process of the fuzzy system design. In: Proceedings of MOSIS'96. Krnov, 1996, pp. 82-87. ISBN 80-85988-02-X. Detail
  • EYSSELT Miloš. The Finite-State Machines Simplified Booth Recodings. In: Proceedings of the 30th Spring International Conference Modelling and Simulation MOSIS'96. April 23-25, Krnov: unknown, 1996, pp. 130-135. ISBN 80-85988-03-8. Detail
  • EYSSELT Miloš. The Perfect Microinstruction Pipeline with Microprogram Counters. In: Proceedings of the Scientific Conference with International Participation ELECTRONIC COMPUTERS & INFORMATICS. September 26-27, Košice-Herĺany: unknown, 1996, pp. 176-181. Detail
  • EYSSELT Miloš. The Petri Net Machines for Signed Digit Recodings. In: Proceedings of the XVIIIth International Workshop Advanced Simulation of Systems ASS 1996. September 17-19, Zábřeh na Moravě: unknown, 1996, pp. 136-141. ISBN 80-85988-10-0. Detail
  • ZENDULKA Jaroslav. The use of VHDL in designing with gate arrays. In: Proceedings of MOSIS'96, Volume 2. Krnov, 1996, pp. 142-147. ISBN 80-85988-03-8. Detail
  • ZENDULKA Jaroslav. Tools for designing with Xilinx FPGAs. In: Proceedings of EDS'96. Brno: Brno University of Technology, 1996, pp. 15-18. ISBN 80-214-0767-8. Detail

1995

  • DVOŘÁK Václav and ŠUSTR Josef. A synthesis of suboptimal decision diagrams. Computer and Artificial Intelligence, vol. 14, no. 1, 1995, pp. 93-103. ISSN 0232-0274. Detail
  • DVOŘÁK Václav. Decomposition techniques for look-up table based FPGA design. In: Proc. of the Workshop on Design Methodologies for Microelectronics. Smolenice: Slovak Academy of Science, 1995, pp. 249-250. Detail
  • DVOŘÁK Václav. Logic decomposition into LUT/MUX-based logic blocks. In: Proceedings of the 7th School VLSI and ASIC Design. Baligrod-Bystre: unknown, 1995, pp. 37-56. ISBN 83-900859-3-3. Detail
  • ZENDULKA Jaroslav. Program for demonstration of ROBDD's. In: Proceedings of EDS'95. Brno: Brno University of Technology, 1995, pp. 201-202. Detail
  • HLAVIČKA Jan, KOTÁSEK Petr and KOTÁSEK Zdeněk. RT Level Test Scheduling Procedure. In: Proceedings on Design Metodologies for Microelectronics. Smolenice: Slovak Academy of Science, 1995, pp. 264-271. Detail
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