Detail projektu

SoC circuits reliability and availability improvement

Období řešení: 1. 1. 2009 – 31. 12. 2011

Typ projektu: grant

Kód: GA102/09/1668

Agentura: Grantová agentura České republiky

Program: Standardní projekty

Název česky
Zvyšování spolehlivost a provozuschopnosti v obvodech SoC
Typ
grant
Klíčová slova

systémy odolné proti poruchám, spolehlivost

Abstrakt

We propose a basic research project that is aimed at utilizing and deepening the
current results of three research groups in the field of on-line and off-line
testing and diagnostics with the intension to utilize them in the design of fault
tolerant systems. The fault tolerant methodologies will be developed on three
levels: level of error tolerance, level of single-event upset detection with
additional reconfiguration and a level of system architecture graceful
degradation in case of unrecoverable faults appearance. The goal of this project
is to design a new, advanced design methodology for fault-tolerant circuits that
will be based on the new technological possibilities.

Řešitelé
Kotásek Zdeněk, doc. Ing., CSc. – hlavní řešitel
Bartoš Pavel, Ing.
Kaštil Jan, Ing., Ph.D.
Mičulka Lukáš, Ing., Ph.D.
Slimařík František, Ing.
Straka Martin, Ing., Ph.D.
Strnadel Josef, Ing., Ph.D. (UPSY)
Publikace

2011

  • BARTOŠ, P. Metody optimalizace propojení scan řetězce. Počítačové architektury a diagnostika 2011. Bratislava: Vydavateľstvo STU, 2011. s. 97-102. ISBN: 978-80-227-3552-0. Detail
  • BARTOŠ, P. Test Time Reduction by Scan Chain Reordering. Proceedings of the 17th Conference STUDENT EEICT 2011. Volume 3. Brno: Faculty of Electrical Engineering and Communication BUT, 2011. p. 564-568. ISBN: 978-80-214-4273-3. Detail
  • BARTOŠ, P.; KOTÁSEK, Z.; DOHNAL, J. Decreasing Test Time by Scan Chain Reorganization. 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Brno University of Technology, 2011. p. 108-108. ISBN: 978-80-214-4305-1. Detail
  • BARTOŠ, P.; KOTÁSEK, Z.; DOHNAL, J. Decreasing Test Time by Scan Chain Reorganization. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011. p. 371-374. ISBN: 978-1-4244-9753-9. Detail
  • MIČULKA, L. Metoda návrh systémů odolných proti poruchám do omezeného implementačního prostoru na bázi FPGA. Počítačové architektury & diagnostika 2011. Bratislava: Fakulta informatiky a informačních technologií Slovenská technická univerzita v Bratislavě, 2011. s. 61-66. ISBN: 978-80-227-3552-0. Detail
  • RUMPLÍK, M.; STRNADEL, J. On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits. Proceedings of the 14th Euromicro Conference on Digital System Design - Architectures, Methods and Tools 2011. Oulu: IEEE Computer Society, 2011. p. 367-374. ISBN: 978-0-7695-4494-6. Detail
  • RŮŽIČKA, R.; ŠIMEK, V. Chip Temperature Selfregulation for Digital Circuits Using Polymorphic Electronics Principles. Proceedings of 14th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2011. p. 205-212. ISBN: 978-0-7695-4494-6. Detail
  • STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems. 14th EUROMICRO Conference on Digital System Design. Oulu: IEEE Computer Society, 2011. p. 223-230. ISBN: 978-0-7695-4494-6. Detail
  • STRAKA, M.; KAŠTIL, J.; NOVOTNÝ, J.; KOTÁSEK, Z. Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011. p. 397-398. ISBN: 978-1-4244-9753-9. Detail
  • STRNADEL, J. Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads. Proceedings of the Work in Progress Session held in connection with SEAA 2011, the 37th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2011, the 14th EUROMICRO Conference on Digital System Design. Oulu: Johannes Kepler University Linz, 2011. p. 21-22. ISBN: 978-3-902457-30-1. Detail
  • STRNADEL, J. Proposal of Flexible Monitoring-Driven HW/SW Interrupt Management for Embedded COTS-Based Event-Triggered Real-Time Systems. Proceedings of the Work-in-Progress Session of the 32nd IEEE Real-Time Systems Symposium. Vienna: Technical University Wien, 2011. p. 29-32. Detail

2010

  • BARTOŠ, P. Optimalizace propojení řetězce scan po ukončení fyzického návrhu. Počítačové architektury a diagnostika 2010. Brno: Fakulta informačních technologií VUT v Brně, 2010. s. 21-26. ISBN: 978-80-214-4140-8. Detail
  • FIŠER, P.; SCHMIDT, J.; VAŠÍČEK, Z.; SEKANINA, L. On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming. Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010. p. 346-351. ISBN: 978-1-4244-6610-8. Detail
  • KOTÁSEK, Z.; ŠKARVADA, J.; STRNADEL, J. Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences. Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010. p. 364-369. ISBN: 978-1-4244-6610-8. Detail
  • KOTÁSEK, Z.; ŠKARVADA, J.; STRNADEL, J. The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. Proceedings of 13th Euromicro Conference on Digital System Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2010. p. 644-651. ISBN: 978-0-7695-4171-6. Detail
  • RŮŽIČKA, R. Gracefully Degrading Circuit Controllers Based on Polytronics. Proc. of 13th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2010. p. 809-812. ISBN: 978-0-7695-4171-6. Detail
  • STRAKA, M. Metodika pro návrh číslicových systémů se zvýšenou spolehlivostí v obvodech FPGA. Počítačové architektury a diagnostika 2010. Brno: Fakulta informačních technologií VUT v Brně, 2010. s. 159-164. ISBN: 978-80-214-4140-8. Detail
  • STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration. 13th EUROMICRO Conference on Digital System Design, DSD'2010. Lille: IEEE Computer Society, 2010. p. 365-372. ISBN: 978-0-7695-4171-6. Detail
  • STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA. NORCHIP 2010. Tampere: IEEE Computer Society, 2010. p. 1-4. ISBN: 978-1-4244-8971-8. Detail
  • STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Methodology for Design of Highly Dependable Systems in FPGA. International Scientific Conference on Computer Science and Engineering. Košice: The University of Technology Košice, 2010. p. 186-193. ISBN: 978-80-8086-164-3. Detail
  • STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs. Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Wien: IEEE Computer Society, 2010. p. 173-176. ISBN: 978-1-4244-6610-8. Detail
  • STRNADEL, J. Task-Level Modeling and Design of Components for Construction of Dependable Time-Critical Systems Implemented by Means of RT Kernel. Sborník přednášek z 33. mezinárodní konference TD 2010 - DIAGON 2010. Zlín: Tomas Bata University in Zlín, 2010. p. 99-104. ISBN: 978-80-7318-940-2. Detail
  • STRNADEL, J. Návrh časově kritických systémů I: specifikace a verifikace. Automa, 2010, roč. 2010, č. 10, s. 42-44. ISSN: 1210-9592. Detail
  • ŠKARVADA, J.; KOTÁSEK, Z.; STRNADEL, J. Optimalizace aplikace testu číslicových systémů pro nízký příkon. Brno: Fakulta informačních technologií VUT v Brně, 2010. 142 s. ISBN: 978-80-214-4209-2. Detail
  • ŠKARVADA, J.; KOTÁSEK, Z.; STRNADEL, J. The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Lecture Notes in Computer Science, ISSN 0302-9743, Vol. 6274. Berlin: Springer Verlag, 2010. p. 181-192. ISBN: 978-3-642-15322-8. ISSN: 0302-9743. Detail

2009

  • KOTÁSEK, Z.; STRAKA, M. The Design of On-line Checkers and Their Use in Verification and Testing. Acta Electrotechnica et Informatica, 2009, vol. 2009, no. 3, p. 8-15. ISSN: 1335-8243. Detail
  • STRAKA, M. Metodologie návrhu obvodů se zvýšenou spolehlivostí založených na FPGA. Počítačové architektury a diagnostika 2009. Zlin: Univerzita Tomáše Bati ve Zlíně, 2009. s. 141-146. ISBN: 978-80-7318-847-4. Detail
  • STRAKA, M.; KOTÁSEK, Z. High Availability Fault Tolerant Architectures Implemented into FPGAs. 12th EUROMICRO Conference on Digital System Design DSD 2009. Patras: IEEE Computer Society, 2009. p. 108-116. ISBN: 978-0-7695-3782-5. Detail
  • STRNADEL, J. Overview of Mechanisms for Improving Reliability of Embedded Real-Time Systems. Proceedings of 32th International Conference TD - DIAGON 2009. Zlín: Tomas Bata University in Zlín, 2009. p. 19-24. ISBN: 978-80-7318-840-5. Detail
Produkty

2010

Nahoru