Project Details

Systém pro programování a realizaci vestavěných systémů

Project Period: 1. 7. 2009 – 30. 6. 2013

Project Type: grant

Code: FR-TI1/038

Agency: Ministerstvo průmyslu a obchodu ČR

Program: TIP

English title
System for Programming and Realization of Embedded Systems
Type
grant
Keywords

Embedded system, software, hardware, microprocessor, compiler, debugger, generator

Abstract

A specification of the embedded system starts with a description of functional and non-functional properties of the system. The specification is updated step by step whith more details. Then it changes into the specification of hardware and software. Based on the software specification a program is created in particular programming language. The hardware specification crosses into the hardware description in hardware description language. After creation of the hardware specification it is a right momentto create tools for programming and debugging of embedded systems software. This step is also crucified in the whole embedded systems design and following development steps would be suitable to automatize. These development steps include a creation of the mentioned tools and a realization of the hardware based on the specification. The task of our project is the automatized generation of mentioned outputs based on the embedded systems specification.

Team members
Masařík Karel, Ing., Ph.D. (CSC) – research leader
Hruška Tomáš, prof. Ing., CSc. (DIFS)
Publications

2013

  • CHARVÁT, L.; SMRČKA, A.; VOJNAR, T. An Abstraction of Multi-Port Memories with Arbitrary Addressable Units. Computer Aided Systems Theory - EUROCAST 2013. Lecture Notes in Computer Science. Berlin Heidelberg: Springer Verlag, 2013. p. 460-468. ISBN: 978-3-642-53855-1. Detail
  • ZACHARIÁŠOVÁ, M.; PŘIKRYL, Z.; HRUŠKA, T.; KOTÁSEK, Z. Automated Functional Verification of Application Specific Instruction-set Processors. IFIP Advances in Information and Communication Technology, 2013, vol. 4, no. 403, p. 128-138. ISSN: 1868-4238. Detail

2012

  • CHARVÁT, L.; SMRČKA, A.; VOJNAR, T. Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description. Proceedings of the 13th International Workshop on Microprocessor Test and Verification (MTV 2012). Austin, TX: Institute of Electrical and Electronics Engineers, 2012. p. 6-12. ISBN: 978-1-4673-4441-8. Detail
  • DOLÍHAL, L.; HRUŠKA, T.; MASAŘÍK, K. Usage of simulators in testing system. Industrial Simulation Conference. Brno: EUROSIS, 2012. p. 74-78. ISBN: 978-90-77381-71-7. Detail
  • DOLÍHAL, L.; HRUŠKA, T.; MASAŘÍK, K. Testing of an automatically generated compiler, Review of retargetable testing system. International Journal on Advances in Software, 2012, vol. 2012, no. 1, p. 15-26. ISSN: 1942-2628. Detail

2011

  • DOLÍHAL, L.; HRUŠKA, T. Porting of C library, Testing of generated compiler. InfoWare 2011. Luxembourg: International Academy, Research, and Industry Association, 2011. p. 125-130. ISBN: 978-1-61208-008-6. Detail
  • ĎURFINA, L.; KŘOUSTEK, J.; ZEMEK, P.; KOLÁŘ, D.; HRUŠKA, T.; MASAŘÍK, K.; MEDUNA, A. Design of a Retargetable Decompiler for a Static Platform-Independent Malware Analysis. The 5th International Conference on Information Security and Assurance. Communications in Computer and Information Science, Volume 200. Brno: Springer Verlag, 2011. p. 72-86. ISBN: 978-3-642-23140-7. Detail
  • ĎURFINA, L.; KŘOUSTEK, J.; ZEMEK, P.; KOLÁŘ, D.; HRUŠKA, T.; MASAŘÍK, K.; MEDUNA, A. Design of a Retargetable Decompiler for a Static Platform-Independent Malware Analysis. International Journal of Security and Its Applications, 2011, vol. 5, no. 4, p. 91-106. ISSN: 1738-9976. Detail
  • KŘOUSTEK, J.; PŘIKRYL, Z.; KOLÁŘ, D.; HRUŠKA, T. Retargetable Multi-level Debugging in HW/SW Codesign. The 23rd International Conference on Microelectronics (ICM 2011). Hammamet: Institute of Electrical and Electronics Engineers, 2011. p. 1-6. ISBN: 978-1-4577-2209-7. Detail
  • KŘOUSTEK, J.; ŽIDEK, S.; KOLÁŘ, D.; MEDUNA, A. Scattered Context Grammars with Priority. International Journal of Advanced Research in Computer Science, 2011, vol. 2, no. 4, p. 1-6. ISSN: 0976-5697. Detail
  • PŘIKRYL, Z. Advanced Methods of Microprocessor Simulation. Information Sciences and Technologies Bulletin of the ACM Slovakia, 2011, vol. 3, no. 3, p. 1-13. ISSN: 1338-1237. Detail
  • PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D. Fast Just-In-Time Translated Simulation for ASIP Design. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Cottbus: IEEE Computer Society, 2011. p. 279-282. ISBN: 978-1-4244-9753-9. Detail
  • PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D. Fast Translated Simulation of ASIPs. OpenAccess Series in Informatics (OASIcs), 2011, vol. 16, no. 1, p. 93-100. ISSN: 2190-6807. Detail
  • PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D.; MASAŘÍK, K.; HUSÁR, A. Design and Simulation of High Performance Parallel Architectures Using the ISAC Language. GSTF International Journal on Computing, 2011, vol. 1, no. 2, p. 97-106. ISSN: 2010-2283. Detail

2010

  • HUSÁR, A.; HRUŠKA, T.; MASAŘÍK, K.; PŘIKRYL, Z. Instruction Pipeline Modeling using Petri Nets. Proceedings of the International Workshop on Petri Nets and Software Engineering - PNSE'10. Proceedings of the International Workshop on Petri Nets and Software. Universität Hamburg: Technical Universityt Hamburg-Harburg, 2010. p. 163-164. ISBN: 978-972-8692-55-1. Detail
  • HUSÁR, A.; HRUŠKA, T.; TRMAČ, M.; PŘIKRYL, Z. Instruction Selection Patterns Extraction from Architecture Specification Language ISAC. Proceedings of the 16th Conference Student EEICT 2010 Volume 5. Brno: Faculty of Information Technology BUT, 2010. p. 166-170. ISBN: 978-80-214-4080-7. Detail
  • HUSÁR, A.; TRMAČ, M.; HRANÁČ, J.; HRUŠKA, T.; MASAŘÍK, K.; KOLÁŘ, D.; PŘIKRYL, Z. Automatic C Compiler Generation from Architecture Description Language ISAC. 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2010. p. 84-91. ISBN: 978-80-87342-10-7. Detail
  • KŘOUSTEK, J.; ŽIDEK, S. Generating Proper VLIW Assembler Code Using Scattered Context Grammars. Proceedings of the 16th Conference Student EEICT 2010 Volume 5. Brno: Faculty of Information Technology BUT, 2010. p. 181-185. ISBN: 978-80-214-4080-7. Detail
  • KŘOUSTEK, J.; ŽIDEK, S.; KOLÁŘ, D.; MEDUNA, A. Exploitation of Scattered Context Grammars to Model VLIW Instruction Constraints. In Proceedings of the 12th Biennial Baltic Electronics Conference. Tallinn: Institute of Electrical and Electronics Engineers, 2010. p. 165-168. ISBN: 978-1-4244-7357-1. Detail
  • PŘIKRYL, Z.; HRUŠKA, T.; MASAŘÍK, K.; HUSÁR, A. Fast Cycle-Accurate Compiled Simulation. 10th IFAC Workshop on Programmable Devices and Embedded Systems, PDeS 2010. Programmable devices and systems. Pszczyna: IFAC, 2010. p. 97-102. ISBN: 978-3-902661-95-1. ISSN: 1474-6670. Detail
  • PŘIKRYL, Z.; HUSÁR, A.; HRUŠKA, T.; MASAŘÍK, K. ASIP Design in the Lissom Project. ACACES 2010 - Poster Abstracts. Ghent: High Performance and Embedded Architecture and Compilation, 2010. p. 105-108. ISBN: 978-90-382-1631-7. Detail
  • PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D. Fast Translated Simulation of ASIPs. 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2010. p. 135-142. ISBN: 978-80-87342-10-7. Detail
  • PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D.; MASAŘÍK, K.; HUSÁR, A. Design and Debugging of Parallel Architectures Using the ISAC Language. Proceedings ot the Annual International Conference on Advanced Distributed and Parallel Computing and Real-Time and Embedded Systems. Singapore: Global Science & Technology Forum, 2010. p. 213-221. ISBN: 978-981-08-7656-2. Detail
  • PŘIKRYL, Z.; MASAŘÍK, K.; HRUŠKA, T.; HUSÁR, A. Generated Cycle-Accurate Profiler for C Language. 13th EUROMICRO Conference on Digital System Design, DSD'2010. Lille: IEEE Computer Society, 2010. p. 263-268. ISBN: 978-0-7695-4171-6. Detail
  • TRMAČ, M.; HUSÁR, A.; HRANÁČ, J.; HRUŠKA, T.; MASAŘÍK, K. Instructor Selector Generation from Architecture Description. 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2010. p. 167-174. ISBN: 978-80-87342-10-7. Detail

2009

  • HUSÁR, A.; PŘIKRYL, Z.; MASAŘÍK, K.; HRUŠKA, T. ASIP Design using Architecture Description Language ISAC. ACACES 2009 - Poster Abstracts. Ghent: High Performance and Embedded Architecture and Compilation, 2009. p. 137-139. ISBN: 978-90-382-1467-2. Detail
  • KŘOUSTEK, J. Code Analysis and Transformation To a High-Level Language. Proceedings of the 15th Conference STUDENT EEICT 2009. Brno: Vysoké učení technické v Brně, 2009. s. 196-198. ISBN: 978-80-214-3868-2. Detail
  • KŘOUSTEK, J. Usage of Decompilation in Processor Architecture Modeling. Proceedings of XXXIth International Autumn Colloquium Advanced Simulation of Systems. Ostrava: 2009. p. 64-67. ISBN: 978-80-86840-47-5. Detail
  • PŘIKRYL, Z.; HRUŠKA, T. Cycle Accurate Profiler for ASIPs. 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2009. p. 168-175. ISBN: 978-80-87342-04-6. Detail
  • PŘIKRYL, Z.; MASAŘÍK, K.; HRUŠKA, T.; HUSÁR, A. Fast Cycle-Accurate Interpreted Simulation. Tenth International Workshop on Microprocessor Test and Verification: Common Challenges and Solutions. Austin: IEEE Computer Society Press, 2009. p. 9-14. ISBN: 978-0-7695-4000-9. Detail
Products

2011

  • ADOP microprocessor, functional specimen, 2011
    Authors: HRUŠKA, T.; MASAŘÍK, K.; FUJCIK, L.; PŘIKRYL, Z.; HUSÁR, A.; PRISTACH, M.
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