Project Details

Navrhování a využívání knihoven aproximativních obvodů

Project Period: 1. 1. 2019 – 31. 12. 2021

Project Type: grant

Code: GA19-10137S

Agency: Czech Science Foundation

Program: Standardní projekty

English title
Designing and exploiting libraries of approximate circuits
Type
grant
Keywords

approximate circuit, computer aided design, genetic programming, evolvable
hardware, digital circuit library

Abstract

Approximate circuits are building blocks of complex systems on a chip that can
exchange the quality of processing for power consumption reduction. The design of
an approximate circuit showing good tradeoffs between the error and other
parameters is still a challenging task. We propose to reduce the design time and
increase the complexity of circuits that can routinely be approximated by (i)
developing a comprehensive library of elementary approximate circuits and (ii)
introducing suitable compositional schemes exploiting the elementary circuits
available in the library. Assembling a complex approximate circuit from
approximate sub-circuits is a challenging problem as it is, in general, unclear
how to perform the (de)composition and how the errors of these sub-circuits
manifest at the global level. The project seeks the following contributions: (1)
efficient deterministic and evolutionary compositional algorithms for approximate
circuit design, (2) a library containing over 1 million approximate circuits, and
(3) new knowledge about approximate circuits by analyzing the library.

Team members
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY) – research leader
Bidlo Michal, doc. Ing., Ph.D. (DCSY)
Drahošová Michaela, Ing., Ph.D. (DCSY)
Husa Jakub, Ing., Ph.D. (DCSY)
Chlebík Jakub, Ing. (DCSY)
Klhůfek Jan, Ing. (DCSY)
Kocnová Jitka, Ing., Ph.D. (RG EHW)
Mrázek Vojtěch, Ing., Ph.D. (DCSY)
Piňos Michal, Ing. (DCSY)
Strnadel Josef, Ing., Ph.D. (DCSY)
Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Publications

2022

  • SEKANINA, L.; VAŠÍČEK, Z.; MRÁZEK, V. Inexact Arithmetic Operators. In Approximate Computing Techniques. Cham: Springer International Publishing, 2022. p. 81-107. ISBN: 978-3-030-94704-0. Detail
  • STRNADEL, J. Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking. In Proceedings of 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Prague: Institute of Electrical and Electronics Engineers, 2022. p. 88-93. ISBN: 978-1-6654-9431-1. Detail

2021

  • BIDLO, M. Evolution of Approximate Functions for Image Thresholding. In IEEE Symposium Series on Computational Intelligence (IEEE SSCI). Los Alamos: IEEE Computer Society, 2021. p. 1-6. ISBN: 978-1-7281-9048-8. Detail
  • CHLEBÍK, J.; JAROŠ, J. Distributed Evolutionary Design of High Intensity Focused Ultrasound Treatment Plans. In IEEE International Conference on Systems, Man and Cybernetics. Melbourne: IEEE Circuits and Systems Society, 2021. p. 2203-2208. ISBN: 978-1-6654-4207-7. Detail
  • HODAŇ, D.; MRÁZEK, V.; VAŠÍČEK, Z. Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. Genetic Programming and Evolvable Machines, 2021, vol. 22, no. 4, p. 539-572. ISSN: 1389-2576. Detail
  • KOCNOVÁ, J.; VAŠÍČEK, Z. Resynthesis of logic circuits using machine learning and reconvergent paths. In 2021 24th Euromicro Conference on Digital System Design (DSD). Palermo: Institute of Electrical and Electronics Engineers, 2021. p. 69-76. ISBN: 978-1-6654-2704-3. Detail
  • MARCHISIO, A.; MRÁZEK, V.; HANIF, M.; SHAFIQUE, M. DESCNet: Developing Efficient Scratchpad Memories for Capsule Network Hardware. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2021, vol. 40, no. 9, p. 1768-1781. ISSN: 1937-4151. Detail
  • MARCHISIO, A.; MRÁZEK, V.; HANIF, M.; SHAFIQUE, M. FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators. IEEE Trans. on VLSI Systems., 2021, vol. 29, no. 4, p. 716-729. ISSN: 1063-8210. Detail
  • STRNADEL, J. Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults. In Proceedings of 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Vienna: Institute of Electrical and Electronics Engineers, 2021. p. 111-114. ISBN: 978-1-6654-3595-6. Detail
  • VAŠÍČEK, Z. Synthesis of approximate circuits for LUT-based FPGAs. In 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Vienna: IEEE Computer Society, 2021. p. 17-22. ISBN: 978-1-6654-3595-6. Detail

2020

  • BIDLO, M. Evolution of Cellular Automata with Conditionally Matching Rules for Image Filtering. In 2020 IEEE Congress on Evolutionary Computation (CEC). Los Alamitos: IEEE Computational Intelligence Society, 2020. p. 1-8. ISBN: 978-1-7281-6929-3. Detail
  • BOSIO, A.; DI CARLO, S.; GIRARD, P.; SANCHEZ, E.; SAVINO, A.; SEKANINA, L.; TRAIOLA, M.; VAŠÍČEK, Z.; VIRAZEL, A. Design, Verification, Test and In-Field Implications of Approximate Computing Systems. In 25th IEEE European Test Symposium. Los Alamitos: Institute of Electrical and Electronics Engineers, 2020. p. 1-10. ISBN: 978-1-7281-4312-5. Detail
  • HUSA, J.; SEKANINA, L. Evolving Cryptographic Boolean Functions with Minimal Multiplicative Complexity. In 2020 IEEE Congress on Evolutionary Computation (CEC). Los Alamitos: IEEE Computational Intelligence Society, 2020. p. 1-8. ISBN: 978-1-7281-6929-3. Detail
  • KOCNOVÁ, J.; VAŠÍČEK, Z. EA-based Resynthesis: An Efficient Tool for Optimization of Digital Circuits. Genetic Programming and Evolvable Machines, 2020, vol. 21, no. 3, p. 287-319. ISSN: 1389-2576. Detail
  • MARCHISIO, A.; MRÁZEK, V.; HANIF, M.; SHAFIQUE, M. ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations. In Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. Grenoble: Institute of Electrical and Electronics Engineers, 2020. p. 1205-1210. ISBN: 978-3-9819263-4-7. Detail
  • MRÁZEK, V.; SEKANINA, L.; VAŠÍČEK, Z. Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2020, vol. 10, no. 4, p. 406-418. ISSN: 2156-3357. Detail
  • MRÁZEK, V.; SEKANINA, L.; VAŠÍČEK, Z. Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. In 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems. Genoa: Institute of Electrical and Electronics Engineers, 2020. p. 243-247. ISBN: 978-1-7281-4922-6. Detail
  • NEVORAL, J.; ŠIMEK, V.; RŮŽIČKA, R. Power Consumption Analysis of New Generation of Polymorphic Gates. In 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020. Novi Sad: Institute of Electrical and Electronics Engineers, 2020. p. 1-6. ISBN: 978-1-7281-9938-2. Detail
  • PRABAKARAN, B.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; SHAFIQUE, M. ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems. In 2020 57th ACM/IEEE Design Automation Conference (DAC). San Francisco: Institute of Electrical and Electronics Engineers, 2020. p. 1-6. ISBN: 978-1-4503-6725-7. Detail
  • STRNADEL, J. Statistical Model Checking of Approximate Circuits: Challenges and Opportunities. In Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). Grenoble: IEEE Computer Society, 2020. p. 1574-1577. ISBN: 978-3-9819263-4-7. Detail
  • VAVERKA, F.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). Grenoble: Institute of Electrical and Electronics Engineers, 2020. p. 294-297. ISBN: 978-3-9819263-4-7. Detail

2019

  • HUSA, J. Comparison of Genetic Programming Methods on Design of Cryptographic Boolean Functions. In Genetic Programming 22st European Conference, EuroGP 2019, Proceedings. Cham: Springer International Publishing, 2019. p. 228-244. ISBN: 978-3-030-14811-9. Detail
  • HUSA, J. Designing Correlation Immune Boolean Functions With Minimal Hamming Weight Using Various Genetic Programming Methods. In GECCO '19 Proceedings of the Genetic and Evolutionary Computation Conference Companion. Praha: Association for Computing Machinery, 2019. p. 342-343. ISBN: 978-1-4503-6748-6. Detail
  • KOCNOVÁ, J.; VAŠÍČEK, Z. EA-based refactoring of mapped logic circuits. In 2019 IEEE International Symposium on Circuits and Systems (ISCAS). Red Hook, NY: IEEE Computer Society Press, 2019. p. 1-5. ISBN: 978-1-7281-0397-6. Detail
  • MRÁZEK, V.; HANIF, M.; VAŠÍČEK, Z.; SEKANINA, L.; SHAFIQUE, M. autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. In The 56th Annual Design Automation Conference 2019 (DAC '19). Las Vegas: Association for Computing Machinery, 2019. p. 1-6. ISBN: 978-1-4503-6725-7. Detail
  • MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; HANIF, M.; SHAFIQUE, M. ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Denver: Institute of Electrical and Electronics Engineers, 2019. p. 1-8. ISBN: 978-1-7281-2350-9. Detail
  • REK, P.; SEKANINA, L. TypeCNN: CNN Development Framework With Flexible Data Types. In Design, Automation and Test in Europe Conference. Florence: European Design and Automation Association, 2019. p. 292-295. ISBN: 978-3-9819263-2-3. Detail
  • VAŠÍČEK, Z. Formal Methods for Exact Analysis of Approximate Circuits. IEEE Access, 2019, vol. 7, no. 1, p. 177309-177331. ISSN: 2169-3536. Detail
  • VAŠÍČEK, Z.; MRÁZEK, V.; SEKANINA, L. Automated Circuit Approximation Method Driven by Data Distribution. In Design, Automation and Test in Europe Conference. Florence: European Design and Automation Association, 2019. p. 96-101. ISBN: 978-3-9819263-2-3. Detail
Products

2019

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