Publication Details

Acceleration of Functional Verification in the Development Cycle of Hardware Systems

ZACHARIÁŠOVÁ Marcela. Acceleration of Functional Verification in the Development Cycle of Hardware Systems. In: Počítačové architektury a diagnostika. Praha: Czech Technical University, 2012, pp. 73-78. ISBN 978-80-01-05106-1.
Czech title
Využití akcelerace funkční verifikaci při vývoji hardwarových systémů
Type
conference paper
Language
english
Authors
Zachariášová Marcela, Ing., Ph.D. (DCSY FIT BUT)
Keywords

functional verification, hardware acceleration, genetic algorithm, optimization

Abstract

Functional verification is a widespread technique for checking whether a hardware system satisfies a given correctness specification. The complexity of modern computer systems is rapidly rising and the verification process takes significant amount of time. It is a challenging process to find appropriate acceleration techniques. I introduce a strategy for acceleration of functional verification using FPGAs by targeting special components of the verification environment to the FPGA.The second approach utilizes genetic algorithm in order to optimize and automate a technique called coverage-driven verification.

Published
2012
Pages
73-78
Proceedings
Počítačové architektury a diagnostika
Conference
Počítačové architektury a diagnostika 2012, PAD 2012, Milovy, CZ
ISBN
978-80-01-05106-1
Publisher
Czech Technical University
Place
Praha, CZ
BibTeX 
@INPROCEEDINGS{FITPUB10139,
   author = "Marcela Zachari\'{a}\v{s}ov\'{a}",
   title = "Acceleration of Functional Verification in the Development Cycle of Hardware Systems",
   pages = "73--78",
   booktitle = "Po\v{c}\'{i}ta\v{c}ov\'{e} architektury a diagnostika",
   year = 2012,
   location = "Praha, CZ",
   publisher = "Czech Technical University",
   ISBN = "978-80-01-05106-1",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/10139"
}
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