Publication Details
Approximate Circuit Design by Means of Evolvable Hardware
approximate circuit, evolutionary design, multiplier, adder
This paper deals with evolutionary design of approximate
circuits. This class of circuits is characterized by relaxing the requirement on functional equivalence between the specification and implementation in order to reduce the area on a chip or minimize energy consumption. We proposed a CGP-based automated design method which enables to find a good trade off between key circuit parameters (functionality, area and power consumption). In particular, the digital approximate circuits consisting of elementary gates are addressed in this paper. Experimental results are provided for combinational single-output circuits and adders where two different metrics are compared for the error assessment.
@INPROCEEDINGS{FITPUB10198, author = "Luk\'{a}\v{s} Sekanina and Zden\v{e}k Va\v{s}\'{i}\v{c}ek", title = "Approximate Circuit Design by Means of Evolvable Hardware", pages = "21--28", booktitle = "2013 IEEE International Conference on Evolvable Systems (ICES)", series = "Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI)", year = 2013, location = "Singapur, SG", publisher = "IEEE Computer Society", ISBN = "978-1-4673-5847-7", doi = "10.1109/ICES.2013.6613278", language = "english", url = "https://www.fit.vut.cz/research/publication/10198" }