Publication Details
Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area
Straka Martin, Ing., Ph.D. (DCSY FIT BUT)
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT)
methodology, partial dynamic reconfiguration, relocation, synchronization, limited redundant space
The paper presents a methodology of fault tolerant system design into an FPGA with the ability of the transient fault and the permanent fault mitigation. The transient fault mitigation is done by the partial dynamic reconfiguration. The mitigation of a certain number of permanent faults is based on using a specific fault tolerant architecture occupiing less resources than the previosly used one and excluding the faulty part of the FPGA. This inovative technique is based on the precompiled configurations stored in an external memory. To reduce the required space for a partial bitstream the relocation technique is used.
@INPROCEEDINGS{FITPUB10374,
author = "Luk\'{a}\v{s} Mi\v{c}ulka and Martin Straka and Zden\v{e}k Kot\'{a}sek",
title = "Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area",
pages = "227--234",
booktitle = "16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools",
year = 2013,
location = "Santander, ES",
publisher = "IEEE Computer Society",
ISBN = "978-0-7695-5074-9",
language = "english",
url = "https://www.fit.vut.cz/research/publication/10374"
}