Hardwarová akcelerace AES-GCM pro protokol SSH

SSH, AES-GCM, hardware acceleration

This paper describes the design of hardware acceleration unit of SSH protocol used for securing network traffic. The unit is to be used as a part of FPGA design on embedded device, thus the design of the unit follows the principles of HW/SW codesign and is supposed to cooperate with modification of existing library implementing mechanisms of SSH protocol. The proposed architecture aims on acceleration of performance heavy computation, namely integrity assurance and encryption over processed data. To complete the goal, encryption algorithm Advanced Encryption Standard (AES) in Galois Counter Mode of operation was chosen, which provides data confidentiality, integrity and authentication. The implemented acceleration unit reaches maximum throughput of 2,4 Gbps at frequency of 100 MHz, though optimalizations are still possible.