Publication Details
CRC based hashing in FPGA using DSP blocks
Kekely Lukáš, Ing., Ph.D. (DCSY FIT BUT)
Puš Viktor, Ing., Ph.D. (CESNET)
FPGA, CRC, DSP, Hash
We propose a novel approach to the computation of the CRC functions, commonly used for bit error checking purposes when handling binary data. This approach is designed for general hashing purposes in FPGA, for which the CRCs are usable as well. The method is suitable for applications which use parallel inputs of fixed size and require high throughput, such as hash tables. We employ the DSP blocks present in modern FPGAs to perform all the necessary XOR operations, so that our solution does not consume any LUTs. We propose a Monte Carlo based heuristic to reduce the number of the DSP blocks required by the computation. Our experimental results show that one DSP block capable of 48 XOR operations can replace around eleven 6-input LUTs.
@INPROCEEDINGS{FITPUB10614,
author = "Tom\'{a}\v{s} Z\'{a}vodn\'{i}k and Luk\'{a}\v{s} Kekely and Viktor Pu\v{s}",
title = "CRC based hashing in FPGA using DSP blocks",
pages = "179--182",
booktitle = "17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems",
year = 2014,
location = "Warszawa, PL",
publisher = "IEEE Computer Society",
ISBN = "978-1-4799-4558-0",
doi = "10.1109/DDECS.2014.6868786",
language = "english",
url = "https://www.fit.vut.cz/research/publication/10614"
}