Result Details

Fast Lookup for Dynamic Packet Filtering in FPGA

KEKELY, L.; ŽÁDNÍK, M.; MATOUŠEK, J.; KOŘENEK, J. Fast Lookup for Dynamic Packet Filtering in FPGA. In Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014. Warszawa: IEEE Computer Society, 2014. p. 219-222. ISBN: 978-1-4799-4558-0.
Type
conference paper
Language
English
Authors
Kekely Lukáš, Ing., Ph.D., DCSY (FIT)
Žádník Martin, Ing., Ph.D., DCSY (FIT)
Matoušek Jiří, Ing., Ph.D., DCSY (FIT)
Kořenek Jan, doc. Ing., Ph.D., DCSY (FIT)
Abstract

Rapidly growing speed and complexity of computer networks impose new requirements on fast lookup structures which are utilized in many networking applications (SDN, firewalls, NATs, etc.). We propose a novel lookup concept based on the well-known cuckoo hashing, which can achieve good memory utilization, supplemented by a binary search tree for offloading the colliding keys and supporting LPM lookup. We also propose a hardware architecture implementing this lookup concept in the FPGA. Our solution is suitable for lookup of the variable-length keys in 100+Gbps networks. Memory utilization of the proposed concept is thoroughly evaluated and it is shown that the concept is scalable to external memory components.

Keywords

Cuckoo hash, binary search, packet filtering, FPGA

Published
2014
Pages
219–222
Proceedings
Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014
Conference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2014
ISBN
978-1-4799-4558-0
Publisher
IEEE Computer Society
Place
Warszawa
DOI
10.1109/DDECS.2014.6868793
UT WoS
000346734200043
EID Scopus
2-s2.0-84938805667
BibTeX 
@inproceedings{BUT111579,
  author="Lukáš {Kekely} and Martin {Žádník} and Jiří {Matoušek} and Jan {Kořenek}",
  title="Fast Lookup for Dynamic Packet Filtering in FPGA",
  booktitle="Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014",
  year="2014",
  pages="219--222",
  publisher="IEEE Computer Society",
  address="Warszawa",
  doi="10.1109/DDECS.2014.6868793",
  isbn="978-1-4799-4558-0",
  url="https://www.fit.vut.cz/research/publication/10615/"
}
Files
Projects
Architektury paralelních a vestavěných počítačových systémů, BUT, Vnitřní projekty VUT, FIT-S-14-2297, start: 2014-01-01, end: 2016-12-31, completed
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, start: 2011-01-01, end: 2015-12-31, completed
Modern Tools for Detection and Mitigation of Cyber Criminality on the New Generation Internet, MV, Program bezpečnostního výzkumu České republiky 2010 - 2015, VG20102015022, start: 2010-10-01, end: 2015-09-30, completed
Research groups
Accelerated Network Technologies Research Group (RG ANT)
Departments
Department of Computer Systems (DCSY)
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