Synchronization Methodology for Fault Tolerant System Recovery After Its Failure

Fault tolerant system, FPGA, state synchronization, recovery, partial dynamic reconfiguration, failure

The paper deals with the topic of a state synchronization for fault tolerant system implemented into SRAM FPGA after its recovery from detected failure. Basic principles of new methodology for solution of synchronization problem are described. Then, methods for the state synchronization for systems based on automatons are presented. Proposed methods are demonstrated on implementation of reconfigurable fault tolerant CAN bus control system.

Modern fault tolerant systems implemented into FPGAs integrate very often hardware redundancy together with fault tolerant approaches based on active fault recovery and the system reconfiguration. An integral part of the recovery process in these systems is except of fault-masking behavior and FPGA partial reconfiguration also the synchronization of reconfigured circuit copy with remaining circuits which are during the recovery process still operating. In the paper, basic principles of our synchronization methodic are described together with generic architecture for synchronization in fault tolerant systems. The usage of the generic architecture for synchronization is demonstrated by its implementation into reconfigurable fault tolerant CAN bus control system.