Publication Details

Akcelerace evolučního návrhu digitálních obvodů na úrovni tranzistorů s využitím platformy Zynq

MRÁZEK Vojtěch. Akcelerace evolučního návrhu digitálních obvodů na úrovni tranzistorů s využitím platformy Zynq. In: Proceedings of the 20th Student Conference, EEICT 2014. Volume 2. Brno: Brno University of Technology, 2014, pp. 229-231. ISBN 978-80-214-4923-7. Available from: http://www.feec.vutbr.cz/EEICT/2014/sbornik/02magisterskeprojekty/10pocitacovesystemy/06-xmraze06@stud.fit.vutbr.cz.pdf
English title
Acceleration of Transistor-Level Evolutionary Design of Digital Circuits Using Zynq
Type
conference paper
Language
czech
Authors
Mrázek Vojtěch, Ing., Ph.D. (DCSY FIT BUT)
URL
Keywords

Cartesian genetic programming, transistor, Zynq, acceleration

Abstract
The objective of this work is to develop a new method for evolutionary design of digital circuits at transistor-level suitable for HW acceleration. As a target platform, a system on chip Xilinx Zynq consisting of ARM and programmable logic is utilized. The proposed accelerator is more than
4x faster than CPU-based implementation with discrete simulation and more than 1000x faster than SPICE-based simulator.
Published
2014
Pages
229-231
Proceedings
Proceedings of the 20th Student Conference, EEICT 2014
Series
Volume 2
Conference
Student EEICT 2014, Brno, CZ
ISBN
978-80-214-4923-7
Publisher
Brno University of Technology
Place
Brno, CZ
BibTeX 
@INPROCEEDINGS{FITPUB10733,
   author = "Vojt\v{e}ch Mr\'{a}zek",
   title = "Akcelerace evolu\v{c}n\'{i}ho n\'{a}vrhu digit\'{a}ln\'{i}ch obvod\r{u} na \'{u}rovni tranzistor\r{u} s vyu\v{z}it\'{i}m platformy Zynq",
   pages = "229--231",
   booktitle = "Proceedings of the 20th Student Conference, EEICT 2014",
   series = "Volume 2",
   year = 2014,
   location = "Brno, CZ",
   publisher = "Brno University of Technology",
   ISBN = "978-80-214-4923-7",
   language = "czech",
   url = "https://www.fit.vut.cz/research/publication/10733"
}
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