Publication Details

Automatic Construction of On-line Checking Circuits Based on Finite Automata

MATUŠOVÁ Lucie, KAŠTIL Jan and KOTÁSEK Zdeněk. Automatic Construction of On-line Checking Circuits Based on Finite Automata. In: 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014, pp. 326-332. ISBN 978-0-7695-5074-9.
Czech title
Automatická konstrukce hlídacích obvodů založených na konečných automatech
Type
conference paper
Language
english
Authors
Matušová Lucie, Ing. (FIT BUT)
Kaštil Jan, Ing. (DCSY FIT BUT)
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT)
Keywords


Fault Tolerant,Active Automata Learning,Online Checkers,Mealy Machine

Abstract

In this paper, the approach to the automatic development of checking circuits for unit implemented in FPGA is described. The checking circuit, also denoted as online checker, introduces fault tolerance aspects to the unit. It provides the information about correctness of the unit output. Checkers are constructed from models inferred by active automata learning which is based on communication with a simulator. To implement the learning environment, LearnLib library has been employed. A platform for automatic construction of online checkers has been designed and implemented. The experimental part of the paper
proves that it is possible to automatically generate the model
for the online checker which describes the basic behaviour of
the checked component. The obtained checker is up to six times
smaller than the original component.

Published
2014
Pages
326-332
Proceedings
17th Euromicro Conference on Digital Systems Design
Conference
17th Euromicro Conference on Digital Systems Design: Architectures, Methods and Tools, Verona, IT
ISBN
978-0-7695-5074-9
Publisher
IEEE Computer Society
Place
Verona, IT
DOI
10.1109/DSD.2014.78
UT WoS
000358409000043
EID Scopus
2-s2.0-84928786780
BibTeX 
@INPROCEEDINGS{FITPUB10734,
   author = "Lucie Matu\v{s}ov\'{a} and Jan Ka\v{s}til and Zden\v{e}k Kot\'{a}sek",
   title = "Automatic Construction of On-line Checking Circuits Based on Finite Automata",
   pages = "326--332",
   booktitle = "17th Euromicro Conference on Digital Systems Design",
   year = 2014,
   location = "Verona, IT",
   publisher = "IEEE Computer Society",
   ISBN = "978-0-7695-5074-9",
   doi = "10.1109/DSD.2014.78",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/10734"
}
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