A Systematic Approach to the Description of Fault-tolerant Systems

As the chip-level integration is rising, the risk of failure is increasing significantly as well. Moreover, the pressure on reliability is also increasing. The growing complexity of digital systems is making the fault-tolerant design of these systems a great challenge. In our work we focus on FPGA (Field Programmable Gate Array) integrated circuits as these are commonly used in a wide range of applications and offer new approaches to fault-tolerant systems design to be used.

Our work focuses on developing a methodology to completely automate the process of fault-tolerant systems design. The method should be based on formal principles. The main idea of the formal approach is to (1) provide an ability to create independent algorithms, which work with well documented data structures and to (2) select and highlight the data that are important for the fault-tolerant systems design.

As the methodology of fault-tolerant systems design automation will be based on formal principles, formal representation of circuit is necessary. The intention of this work is to formalize the description of a digital circuit and show some algorithms that make use of the mentioned description, especially algorithms used for transformation of the model of digital circuit into its fault-tolerant version.