Publication Details
Evoluční snižování příkonu: Od obvodů na úrovni tranzistorů po neuronové sítě na čipu
MRÁZEK Vojtěch. Evoluční snižování příkonu: Od obvodů na úrovni tranzistorů po neuronové sítě na čipu. In: Počítačové architektury a diagnostika PAD 2016. Bořetice: Faculty of Information Technology BUT, 2016, pp. 61-64. ISBN 978-80-214-5376-0.
English title
Evolutionary reduction of power consumption: From transistor-level circuits till neural networks on the chip
Type
conference paper
Language
czech
Authors
Mrázek Vojtěch, Ing., Ph.D. (DCSY FIT BUT)
Keywords
power consumption
evolutionary design
neural networks
median filter
sorting networks
Abstract
The decreasing of power consumption becomes to be very important. The aim of this work is to utilise evolutionary algorithms in order to optimisation of the power consumption of digital circuits. It focus on the application of the algorithms in the real-world problems. Four applications were selected to show the ability of the proposed algorithms to decrease the power. New modules described on the transistor-level were designed, the power consumption of median filters were reduced, the new methods of approximate sorting were shown and the new approach for approximation in neural networks was introduced.
Published
2016
Pages
61-64
Proceedings
Počítačové architektury a diagnostika PAD 2016
Conference
Počítačové architektury a diagnostika 2016, Bořetice, CZ
ISBN
978-80-214-5376-0
Publisher
Faculty of Information Technology BUT
Place
Bořetice, CZ
BibTeX
@INPROCEEDINGS{FITPUB11194,
author = "Vojt\v{e}ch Mr\'{a}zek",
title = "Evolu\v{c}n\'{i} sni\v{z}ov\'{a}n\'{i} p\v{r}\'{i}konu: Od obvod\r{u} na \'{u}rovni tranzistor\r{u} po neuronov\'{e} s\'{i}t\v{e} na \v{c}ipu",
pages = "61--64",
booktitle = "Po\v{c}\'{i}ta\v{c}ov\'{e} architektury a diagnostika PAD 2016",
year = 2016,
location = "Bo\v{r}etice, CZ",
publisher = "Faculty of Information Technology BUT",
ISBN = "978-80-214-5376-0",
language = "czech",
url = "https://www.fit.vut.cz/research/publication/11194"
}
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