Detail výsledku
Towards Low Power Approximate DCT Architecture for HEVC Standard
Mrázek Vojtěch, Ing., Ph.D., UPSY (FIT)
Sekanina Lukáš, prof. Ing., Ph.D., UPSY (FIT)
Video processing performed directly on IoT nodesis one of the most performance as well as energy demandingapplications for current IoT technology. In order to support realtimehigh-definition video, energy-reduction optimizations haveto be introduced at all levels of the video processing chain. Thispaper deals with an efficient implementation of Discrete CosineTransform (DCT) blocks employed in video compression basedon the High Efficiency Video Coding (HEVC) standard. The proposed multiplierless 4-input DCT implementations contain approximate adders and subtractors that were obtained usinggenetic programming. In order to manage the complexity ofevolutionary approximation and provide formal guarantees interms of errors of key circuit components, the worst and averageerrors were determined exactly by means of Binary decisiondiagrams. Under conditions of our experiments, approximate 4-input DCTs show better quality/power trade-offs than relevantimplementations available in the literature. For example, 25%power reduction for the same error was obtained in comparisonwith a recent highly optimised implementation.
Genetic programming, relaxed equivalence, approximate computing, HEVC, DCT
@inproceedings{BUT134715,
author="Zdeněk {Vašíček} and Vojtěch {Mrázek} and Lukáš {Sekanina}",
title="Towards Low Power Approximate DCT Architecture for HEVC Standard",
booktitle="Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)",
year="2017",
pages="1576--1581",
publisher="European Design and Automation Association",
address="Lausanne",
doi="10.23919/DATE.2017.7927241",
isbn="978-3-9815370-9-3",
url="https://www.fit.vut.cz/research/publication/11299/"
}