Publication Details

Mapping of P4 Match Action Tables to FPGA

KEKELY Michal and KOŘENEK Jan. Mapping of P4 Match Action Tables to FPGA. In: Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS. Ghent: Institute of Electrical and Electronics Engineers, 2017, pp. 1-2. ISBN 978-90-90-30428-1.
Czech title
Mapování P4 vyhledávacích tabulek do FPGA
Type
conference paper
Language
english
Authors
Kekely Michal, Ing. (DCSY FIT BUT)
Kořenek Jan, doc. Ing., Ph.D. (DCSY FIT BUT)
Keywords

P4, FPGA, packet classification, match action tables

Abstract

Current networks are changing very fast. Network administrators need

more flexible and powerful tools to be able to support new protocols or services very fast. The P4 language provides new level of abstraction for flexible packet processing. Therefore, we have designed new architecture for memory efficient mapping of P4 match/action tables to FPGA. The architecture is based on DCFL algorithm and is able to balance the processing speed and available memory resources.
Published
2017
Pages
1-2
Proceedings
Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS
Conference
27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, Ghent, BE
ISBN
978-90-90-30428-1
Publisher
Institute of Electrical and Electronics Engineers
Place
Ghent, BE
DOI
10.23919/FPL.2017.8056768
UT WoS
000426989400013
EID Scopus
2-s2.0-85034425205
BibTeX 
@INPROCEEDINGS{FITPUB11551,
   author = "Michal Kekely and Jan Ko\v{r}enek",
   title = "Mapping of P4 Match Action Tables to FPGA",
   pages = "1--2",
   booktitle = "Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS",
   year = 2017,
   location = "Ghent, BE",
   publisher = "Institute of Electrical and Electronics Engineers",
   ISBN = "978-90-90-30428-1",
   doi = "10.23919/FPL.2017.8056768",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/11551"
}
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