Publication Details
High-Speed Computation of CRC Codes for FPGAs
Cabal Jakub, Ing. (CESNET)
Kořenek Jan, doc. Ing., Ph.D. (DCSY FIT BUT)
Cyclic Redundancy Check, CRC, FPGA, Ethernet, high-speed networks
As the throughput of networks and memory interfaces is on a constant rise, there is a need for ever-faster error-detecting codes. Cyclic redundancy checks (CRC) are a common and widely used to ensure consistency or detect accidental changes of data. We propose a novel FPGA architecture for the computation of the CRC designed for general high-speed data transfers. Its key feature is allowing a processing of multiple independent data packets (transactions) in each clock cycle, what is a necessity for achieving high overall throughput on very wide data buses. Experimental results confirm that the proposed architecture reaches an effective throughput sufficient for utilization in multi-terabit Ethernet networks (over 2 Tbps or over 3000 Mpps) on a single Xilinx UltraScale+ FPGA.
@INPROCEEDINGS{FITPUB11888,
author = "Luk\'{a}\v{s} Kekely and Jakub Cabal and Jan Ko\v{r}enek",
title = "High-Speed Computation of CRC Codes for FPGAs",
pages = "237--240",
booktitle = "Proceedings of the 2018 International Conference on Field-Programmable Technology (FPT 2018)",
year = 2018,
location = "Naha, JP",
publisher = "IEEE Computer Society",
ISBN = "978-1-7281-0214-6",
doi = "10.1109/FPT.2018.00042",
language = "english",
url = "https://www.fit.vut.cz/research/publication/11888"
}