Nové metody optimalizace interpretace scénářů portovatelných stimulů

portable stimulus, functional verification, processors

The ever-increasing complexity of hardware designs requires not only continuous improvement of design techniques and procedures, but also functional verification that has become an integral part of the process. One of the innovations bringing potential improvements in functional verification is Accellera's standard for portable stimulus. The aim of this work is to support the use of the new standard by various extensions. The first step is to create design patterns that facilitate portability between abstraction levels. Furthermore, the aim is to create linking system that will allow the verification scenarios from higher level of abstraction target specific areas (IP blocks) of the system under verification. The third step is to automate verification using a machine learning algorithm. The final step is to use the linking system to focus the machine learning algorithm on a specific area of the system under verification.