Publication Details
Statistical Model Checking of Approximate Circuits: Challenges and Opportunities
approximate circuit, error, trade-off, relaxed equivalence, formal verification, timed automaton, stochastic automaton, modeling, simulation, statistical model checking
Many works have shown that approximate circuits may play an important role in the development of resource-efficient electronic systems. This motivates many researchers to propose new approaches for finding an optimal trade-off between the approximation error and resource savings for predefined applications of approximate circuits. The works and approaches, however, focus mainly on design aspects regarding relaxed functional requirements while neglecting further aspects such as signal and parameter dynamics/stochasticity, relaxed/non-functional equivalence, testing or formal verification. This paper aims to take a step ahead by moving towards the formal verification of time-dependent properties of systems based on approximate circuits. Firstly, it presents our approach to modeling such systems by means of stochastic timed automata whereas our approach goes beyond digital, combinational and/or synchronous circuits and is applicable in the area of sequential, analog and/or asynchronous circuits as well. Secondly, the paper shows the principle and advantage of verifying properties of modeled approximate systems by the statistical model checking technique. Finally, the paper evaluates our approach and outlines future research perspectives.
@INPROCEEDINGS{FITPUB12055,
author = "Josef Strnadel",
title = "Statistical Model Checking of Approximate Circuits: Challenges and Opportunities",
pages = "1574--1577",
booktitle = "Proceedings of the 2020 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)",
year = 2020,
location = "Grenoble, FR",
publisher = "IEEE Computer Society",
ISBN = "978-3-9819263-4-7",
doi = "10.23919/DATE48585.2020.9116207",
language = "english",
url = "https://www.fit.vut.cz/research/publication/12055"
}