Publication Details

Scalable P4 Deparser for Speeds Over 100 Gbps

CABAL Jakub, BENÁČEK Pavel, FOLTOVÁ Jana and HOLUB Juraj. Scalable P4 Deparser for Speeds Over 100 Gbps. Annual IEEE Symposium on Field-Programmable Custom Computing Machines. Los Alamitos, 2019. ISBN 978-1-7281-1131-5. Available from: https://ieeexplore.ieee.org/document/8735524
Czech title
Škálování P4 deparseru při rychostech vyšších než 100 Gbps
Type
abstract
Language
english
Authors
Cabal Jakub, Ing. (CESNET)
Benáček Pavel, Ing. (CESNET)
Foltová Jana, Mgr. (CESNET)
Holub Juraj, Ing. (FIT BUT)
URL
Keywords

field programmable gate arrays (FPGA), high speed networks, 100gbps, building blockes, deparser, network devices, P4 language, packet processing, packet-based, scalable architectures, computers

Abstract

The P4 language is a language suitable for the description of packet processing inside a network device. The typical P4 device consists of three main building blocks: Parser, Match+Action Tables and Deparser. The deparsing is the most challenging block because the main task of this block is to assemble the output packet based on changes in Match+Action Tables. This operation can be quite complicated in the case of high-speed networks. In this work, we present the scalable architecture (in term of the throughput) of a deparsing circuit which is suitable for implementation in FPGAs.

Published
2019
Pages
323-323
Book
Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Conference
The 27th IEEE International Symposium On Field-Programmable Custom Computing Machines -- FCCM'19, San Diego, CA, US
ISBN
978-1-7281-1131-5
Place
Los Alamitos, US
DOI
10.1109/FCCM.2019.00064
UT WoS
000491873200055
EID Scopus
2-s2.0-85068311347
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