Pipelined ALU for effective external memory access in FPGA

The external memories in digital design are closelyrelated to high response time. The most common approach tomitigate latency is adding a caching mechanism into the memorysubsystem. This solution might be sufficient in CPU architecture,where we can reschedule operations when a cache miss occurs.However, the FPGA architectures are usually accelerators withsimple functionality, where it is not possible to postpone work.The cache miss often leads to whole pipeline stall or even todata loss. The architecture we present in this paper reducesthis problem by aggregating arithmetic operations into thememory subsystem itself. Fast data processing is achieved becausearithmetic operations working with external data are offloaded.Our architecture reaches a speed of 200 Mp/s (operations carriedout). It is designed to be used in systems with link speeds of100 Gb/s. It outperforms other implementations by a factor of atleast 3. The additional benefit of our architecture is reducing thenumber of memory transactions by a factor of two on real-worlddatasets.