Accelerating Tests of Arithmetic Circuits Through On-FPGA Stimuli Generation and Their Reduction

Fault-tolerant System Design Evaluation, Fault Tolerance Property Estimation, Functional Verification, High-level Synthesis, Test Bed Generation

This paper evaluates the possibility to accelerate fault tolerance evaluation of arithmetic circuits through reduced stimuli. In our research, we used a simplistic on-chip stimuli generator producing numbers in a row with a certain step (i.e. every nth number). The results are obtained through experimentation on a real HW Field Programmable Gate Array. The results confirm the hypothesis, that there might exist appropriate settings, for which the critical bit detection precision becomes only slightly worse but the reliability verification will accelerate significantly. Thus, the correct detection of critical bits in relation to step size is evaluated as certain steps provide significantly lower precision of the estimation than others. Our data show that the steps of sizes larger than 30 do not provide any further effective acceleration. In this paper, evaluations requiring error rate per fault injection are also considered. We also propose a novel stair chart to illustrate the measurement of the error rate per each fault. The results show that the size of the circuit had a minimal impact on the precision. General conclusion is that, by tuning the proper settings of the simplistic generator, significant acceleration of the evaluation can be achieved. The low area overhead of the reduced stimuli generator leaves the saved resources to the tested unit, which in the case of parallel evaluation further supports the acceleration.