Publication Details
Web-Based Simulator of Superscalar RISC-V Processors
JAROŠ Jiří, MAJER Michal, HORKÝ Jakub and VÁVRA Jan. Web-Based Simulator of Superscalar RISC-V Processors. Atlanta, GA, 2024. Available from: https://sc24.supercomputing.org/proceedings/poster/poster_files/post150s2-file3.pdf
Czech title
Webový simulátor superskalárních procesorů RISC-V
Type
presentation,poster
Language
english
Authors
Jaroš Jiří, doc. Ing., Ph.D. (DCSY FIT BUT)
Majer Michal, Ing. (FIT BUT)
Horký Jakub, Ing. (FIT BUT)
Vávra Jan, Ing. (FIT BUT)
Majer Michal, Ing. (FIT BUT)
Horký Jakub, Ing. (FIT BUT)
Vávra Jan, Ing. (FIT BUT)
URL
Keywords
Web-based simulator, RISC-V processor, superscalar processor
Abstract
Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar processors and HW-SW co-design. With customizable processor architecture, full C compiler support, and detailed performance statistics, this tool offers a comprehensive learning experience. Enjoy the convenience of a modern, web-based GUI to enhance your understanding and skills.
Published
2024
Pages
1-2
Conference
The International Conference for High Performance Computing, Networking, Storage, and Analysis, Georgia World Congress Center, Atlanta,Georgia, US
Place
Atlanta, GA, US