Publication Details
CSP-based Modeling of SM Architectures
Shared memory, CSP, Transim, performance comparison
The possibility of modeling of shared memory (SM) architectures using communicating sequential processes (CSP) is described. The CSP-based Transim tool enabled us to perform fair performance comparison of theoretical PRAM model and the message passing (MP) model on one hand and the real bus based SM systems with coherent caches on the other. Various memory update strategies, cache coherence protocols and bus arbitration strategies have been examined, such as write through/write back memory update, write invalidate/write update cache coherence protocols, and the most frequently used bus arbitration strategies (fair, priority-based, random). For comparison we have chosen parallel solution of a large system of linear equations. Performance results are presented and discussed.
Modeling of shared memory (SM) architectures using CSP-based Transim tool is described. It made possible fair performance comparison of real bus based cache-coherent SM systems, DM systems with message passing and PRAM models.
@INPROCEEDINGS{FITPUB5664,
author = "Rudolf \v{C}ejka and V\'{a}clav Dvo\v{r}\'{a}k",
title = "CSP-based Modeling of SM Architectures",
pages = "163--168",
booktitle = "Proceedings of conference Computer Engineering and Informatics CE\&I'99",
year = 1999,
location = "Kosice - Herlany, SK",
publisher = "Faculty of Electrical Engineering and Informatics, University of Technology Ko\v{s}ice",
ISBN = "80-88922-05-4",
language = "english",
url = "https://www.fit.vut.cz/research/publication/5664"
}