Publication Details
Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study
DVOŘÁK Václav. Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study. In: Proceedings of the the International Workshop on Discrete-Event System Design, DESDes'01. Przytok near Zielona Gora, POLAND: Publishing House of Zielona Gora Technical University, 2001, pp. 103-108. ISBN 83-85911-62-6.
Type
conference paper
Language
english
Authors
Dvořák Václav, Prof. Ing., DrSc. (DCSE FEECS BUT)
Keywords
Parallel Embedded Systems, Multiprocessor Simulation, Hardware Description Language
Abstract
The paper addresses the issue of prototyping hw/sw architecture of application-specific multi-processor systems (recently on a chip). Performance prediction of these systems, either bus-based SMPs or message-passing networks of DSPs, is undertaken using a CSP-based tool Transim. Variations in processor count, clock rate, link speed, bus bandwidth, cache line, as well as in partitioning and mapping the resulting sw components to processors can be easily accounted for. The technique is demonstrated on parallel FFT on 2 to 8 processors.
Published
2001
Pages
103-108
Proceedings
Proceedings of the the International Workshop on Discrete-Event System Design, DESDes'01
Conference
The International Workshop on Discrete-Event System Design, DESDes'01, Przytok near Zielona Gora, PL
ISBN
83-85911-62-6
Publisher
Publishing House of Zielona Gora Technical University
Place
Przytok near Zielona Gora, POLAND, PL
BibTeX
@INPROCEEDINGS{FITPUB5672,
author = "V\'{a}clav Dvo\v{r}\'{a}k",
title = "Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study",
pages = "103--108",
booktitle = "Proceedings of the the International Workshop on Discrete-Event System Design, DESDes'01",
year = 2001,
location = "Przytok near Zielona Gora, POLAND, PL",
publisher = "Publishing House of Zielona Gora Technical University",
ISBN = "83-85911-62-6",
language = "english",
url = "https://www.fit.vut.cz/research/publication/5672"
}