Publication Details

RT Level Test Scheduling

BLATNÝ, J., KOTÁSEK, Z. RT Level Test Scheduling. Computer and Artificial Intelligence, vol. 14, no. 1, 1997, p. 13 ( p.)ISSN: 0232-0274.
Type
journal article
Language
English
Authors
Blatný Jan, prof. Ing., DrSc.
Hlavička Jan
Kotásek Zdeněk, doc. Ing., CSc.
Annotation

The paper describes a new model of exploiting parallelism in testing VLSI circuits. The model utilizes the concept of TACG (Test Application Conflict Graph). For the testing process the resource utilization model was defined and used for the TACG construction. Different conflicts that must be taken into account during an RTL circuit test scheduling sre presented. The problem of concurrent test application is transformed to the one of TACG coloring and covering its nodes. Thus, the graph theory algorithms can be utilized for an RT level test scheduling. Different conflicts that must be considered during the RT level test scheduling are discussed. The way how to use the TACG for an RTL circuit modification is also presented. The paper offers a methodology that can be utilized during VLSI circuit design process, the goal of which is to reduce the overall test application time of an RTL circuit.

Published
Pages
1
Journal
Computer and Artificial Intelligence, vol. 14, no. 1, 1997, ISSN 0232-0274
BibTeX
@article{BUT39067,
  author="Jan {Blatný} and Jan {Hlavička} and Zdeněk {Kotásek}",
  title="RT Level Test Scheduling",
  journal="Computer and Artificial Intelligence",
  volume="14",
  number="1, 1997",
  pages="1",
  issn="0232-0274"
}
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