Publication Details

RT Level Test Scheduling Procedure

HLAVIČKA Jan, KOTÁSEK Petr and KOTÁSEK Zdeněk. RT Level Test Scheduling Procedure. In: Proceedings on Design Metodologies for Microelectronics. Smolenice: Slovak Academy of Science, 1995, pp. 264-271.
Type
conference paper
Language
english
Authors
Hlavička Jan, Prof. Ing., DrSc. (FEE CTU)
Kotásek Petr, Ing. (DCSE FEECS BUT)
Kotásek Zdeněk, Doc. Ing., CSc. (DCSE FEECS BUT)
Keywords

Design for Testability, built-in-self test, test scheduling, graph coloring

Annotation

It is shown how the problem of concurrent test application can be transformed to the one of Test Application Conflict Graph coloring and covering its nodes. Different conflicts, that appear during an RTL circuit test scheduling, can be taken into account. One of them, the test application time of different units, is discussed in details. It is also shown how the TACG concept can be utilized for a test scheduling of tests with unequal test length.

Published
1995
Pages
264-271
Proceedings
Proceedings on Design Metodologies for Microelectronics
Publisher
Slovak Academy of Science
Place
Smolenice, SK
BibTeX 
@INPROCEEDINGS{FITPUB6038,
   author = "Jan Hlavi\v{c}ka and Petr Kot\'{a}sek and Zden\v{e}k Kot\'{a}sek",
   title = "RT Level Test Scheduling Procedure",
   pages = "264--271",
   booktitle = "Proceedings on Design Metodologies for Microelectronics",
   year = 1995,
   location = "Smolenice, SK",
   publisher = "Slovak Academy of Science",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/6038"
}
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