Publication Details

Design of the Special Fast Reconfigurable Chip Using Common FPGA

SEKANINA Lukáš and RŮŽIČKA Richard. Design of the Special Fast Reconfigurable Chip Using Common FPGA. In: Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000. Smolenice: unknown, 2000, pp. 161-168. ISBN 80-968320-3-4.
Czech title
Návrh speciálního rychle rekonfigurovatelného obvodu s využitím běžného FPGA
Type
conference paper
Language
english
Authors
Sekanina Lukáš, Ing. (DCSE FEECS BUT)
Růžička Richard, Ing. (DCSE FEECS BUT)
URL
Keywords

reconfigurable circuits, evolvable hardware

Abstract

Some applications require chips with fast partial reconfiguration. These requirements are traditionally satisfied by a special chip design, but it is usually a very expensive solution. This paper describes a new approach. Special fast partially reconfigurable chip is implemented with a common FPGA. The format of the configuration bit stream is suggested and optimized according to the given task. Result chip offers many good properties, but some problems with scalability can appear.

Annotation
Published
2000
Pages
161-168
Proceedings
Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000
Conference
Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000, Smolenice, Slovakia, SK
ISBN
80-968320-3-4
Place
Smolenice, SK
BibTeX 
@INPROCEEDINGS{FITPUB6394,
   author = "Luk\'{a}\v{s} Sekanina and Richard R\r{u}\v{z}i\v{c}ka",
   title = "Design of the Special Fast Reconfigurable Chip Using Common FPGA",
   pages = "161--168",
   booktitle = "Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000",
   year = 2000,
   location = "Smolenice, SK",
   ISBN = "80-968320-3-4",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/6394"
}
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