Detail publikace

Test Overhead Reduction through RT Level Testability Analysis

HLAVIČKA Jan, KOTÁSEK Zdeněk a ZBOŘIL František. Test Overhead Reduction through RT Level Testability Analysis. In: Proceedings of the IEEE ETW 1997. Cagliary: neznámá, 1997, s. 43-47.
Název česky
Test Overhead Reduction through RT Level Testability Analysis
Typ
článek ve sborníku konference
Jazyk
angličtina
Autoři
Hlavička Jan, Prof. Ing., DrSc. (FEL ČVUT)
Kotásek Zdeněk, Doc. Ing., CSc. (UIVT-VVS FEI VUT)
Zbořil František, Doc. Ing., CSc. (UIVT FEI VUT)
Klíčová slova

Design for Testability, RT Level Testability Analysis, RT Level Element Classification, Test Application

Abstrakt

The paper presents a new method of formal testability analysis made on the RT level in PROLOG environment. This analysis is based on a model which classifies the RT level elements into categories by their function during the testing. The results of the analysis are used for designing a combined test mode in which elements accessible through I-paths are tested with a sequence of parallel test vectors whereas the serial scan method is used only for the remaining elements. This leads to savings both in test application time and in chip area overhead.

Rok
1997
Strany
43-47
Sborník
Proceedings of the IEEE ETW 1997
Konference
IEEE ETW'97 (European Test Workshop), Cagliary, IT
Vydavatel
neznámá
Místo
Cagliary, IT
BibTeX 
@INPROCEEDINGS{FITPUB6594,
   author = "Jan Hlavi\v{c}ka and Zden\v{e}k Kot\'{a}sek and Franti\v{s}ek Zbo\v{r}il",
   title = "Test Overhead Reduction  through RT Level Testability Analysis",
   pages = "43--47",
   booktitle = "Proceedings of the IEEE ETW 1997",
   year = 1997,
   location = "Cagliary, IT",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/6594"
}
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