Detail publikace

RT Level Testability Analysis In PROLOG Enviroment

KOTÁSEK Zdeněk a ZBOŘIL František. RT Level Testability Analysis In PROLOG Enviroment. In: Proceedings of the DDECS'97. Ostrava: MARQ, 1997, s. 47-52. ISBN 80-85988-19-4.
Název česky
RT Level Testability Analysis In PROLOG Enviroment
Typ
článek ve sborníku konference
Jazyk
angličtina
Autoři
Kotásek Zdeněk, Doc. Ing., CSc. (UIVT-VVS FEI VUT)
Zbořil František, Doc. Ing., CSc. (UIVT FEI VUT)
Klíčová slova

RT Level Testability Analysis, RTL Circuit Transformation, PROLOG

Abstrakt

The paper deals with the principles of the RT level testability analysis. The prescription for an RTL circuit transformation to a labelled directed graph and its representation in PROLOG environment are presented. The methodology for the RT level testability analysis and the principles of its implementation are described in detail.

Rok
1997
Strany
47-52
Sborník
Proceedings of the DDECS'97
Konference
Int. Conf. on DDECS'97, Soláň, CZ
ISBN
80-85988-19-4
Vydavatel
MARQ
Místo
Ostrava, CZ
BibTeX 
@INPROCEEDINGS{FITPUB6595,
   author = "Zden\v{e}k Kot\'{a}sek and Franti\v{s}ek Zbo\v{r}il",
   title = "RT Level Testability Analysis In  PROLOG Enviroment",
   pages = "47--52",
   booktitle = "Proceedings of the  DDECS'97",
   year = 1997,
   location = "Ostrava, CZ",
   ISBN = "80-85988-19-4",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/6595"
}
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