Publication Details

RT Level Testability Analysis In PROLOG Enviroment

KOTÁSEK Zdeněk and ZBOŘIL František. RT Level Testability Analysis In PROLOG Enviroment. In: Proceedings of the DDECS'97. Ostrava, 1997, pp. 47-52. ISBN 80-85988-19-4.
Czech title
RT Level Testability Analysis In PROLOG Enviroment
Type
conference paper
Language
english
Authors
Kotásek Zdeněk, Doc. Ing., CSc. (DCSE FEECS BUT)
Zbořil František, Doc. Ing., CSc. (DCSE FEECS BUT)
Keywords

RT Level Testability Analysis, RTL Circuit Transformation, PROLOG

Abstract

The paper deals with the principles of the RT level testability analysis. The prescription for an RTL circuit transformation to a labelled directed graph and its representation in PROLOG environment are presented. The methodology for the RT level testability analysis and the principles of its implementation are described in detail.

Published
1997
Pages
47-52
Proceedings
Proceedings of the DDECS'97
Conference
Int. Conf. on DDECS'97, Soláň, CZ
ISBN
80-85988-19-4
Place
Ostrava, CZ
BibTeX 
@INPROCEEDINGS{FITPUB6595,
   author = "Zden\v{e}k Kot\'{a}sek and Franti\v{s}ek Zbo\v{r}il",
   title = "RT Level Testability Analysis In  PROLOG Enviroment",
   pages = "47--52",
   booktitle = "Proceedings of the  DDECS'97",
   year = 1997,
   location = "Ostrava, CZ",
   ISBN = "80-85988-19-4",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/6595"
}
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